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TPS650940 Datasheet(PDF) 4 Page - Texas Instruments |
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TPS650940 Datasheet(HTML) 4 Page - Texas Instruments |
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4 / 92 page  4 TPS65094, TPS650940, TPS650941, TPS650942, TPS650944 SWCS133A – SEPTEMBER 2015 – REVISED JUNE 2016 www.ti.com Submit Documentation Feedback Product Folder Links: TPS65094 Revision History Copyright © 2015–2016, Texas Instruments Incorporated 2 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from September 11, 2015 to June 2, 2016 (from * Revision (September 2015) to A Revision) Page • Released full data sheet ............................................................................................................ 1 • Changed device status to PROD_DATA .......................................................................................... 1 • Changed VIN recommended minimum ............................................................................................. 1 • Changed Features to improve description of converters ....................................................................... 1 • Changed Features to up to 400 mA of output current for load switches ...................................................... 1 • Changed Description for broader scope .......................................................................................... 1 • Changed the Functional Block Diagram to include an inverter on PROCHOT pin ........................................... 2 • Changed functional block diagram to include TPS65094x family ............................................................. 2 • Changed PROCHOTB to PROCHOT throughout the document ............................................................... 6 • Changed minimum absolute-maximum-rating value for SW1, SW2, and SW6 in Section 5.1 ............................ 10 • Changed VSYS in Section 5.3, Recommended Operating Conditions ...................................................... 11 • Deleted nominal value from PVINVTT in Section 5.3, Recommended Operating Conditions ........................... 11 • Deleted (nu = symbol for efficiency) ............................................................................................. 13 • Changed BUCK1 DC output voltage step size to show full range and be consistent in Section 5.7 .................... 13 • Changed typo to match correct default of 1 V for ΔVOUT_TR in Section 5.7 ................................................. 13 • Changed BUCK2 DC output voltage to show full range and be consistent in Section 5.7 ................................ 14 • Changed set condition for BUCK6 for VOUT range in Section 5.7 to match BUCK1 and BUCK2 ........................ 15 • Updated formatting and added new OTP information for BUCK6 in Section 5.7 ........................................... 15 • Updated formatting for BUCK3 DC output voltage in Section 5.8 ............................................................ 17 • Changed DC output voltage formatting for BUCK4 in Section 5.8 ........................................................... 18 • Changed maximum IOUT value for BUCK4 in Section 5.8 to match device capabilities ................................... 18 • Changed IOUT and ΔVOUT/ΔIOUT for VTT LDO in Section 5.9 for new OTPs ................................................ 23 • Changed test conditions for VTT LDO overcurrent protection in Section 5.9 ............................................... 23 • Changed Section 5.10 to show SWB1_2 RDSON is specified per output .................................................... 24 • Changed fSW values in Section 5.15 to provide more values ................................................................. 26 • Changed current to 1.9 A to match SoC requirements in Table 6-1 ......................................................... 28 • Changed BUCK6, LDOA2, LDOA3 typical output voltage range to: OTP Dependent in Table 6-1 ...................... 28 • Changed table note to include additional DDR types in Table 6-1 ........................................................... 28 • Changed PMIC Functional Block Diagram to match specifications table ................................................... 29 • Changed PROCHOTB to PROCHOT in the Apollo Lake Power Map ....................................................... 30 • Changed current ratings in Apollo Lake Power Map ........................................................................... 30 • Deleted SWBx PG from PG of PCH_PWROK in Table 6-2 ................................................................... 31 • Changed BUCK1–2 to all BUCKs and LDOAs in Section 6.4.3.3 ............................................................ 36 • Added Table 6-5 and Table 6-6 to Section 6.4.4.2 ............................................................................. 38 • Added more DDR values to the table note in Table 6-7 ....................................................................... 39 • Changed Section 6.4.5 to include LDOA1 and reset information ............................................................. 40 • Changed Section 6.7 to include multiple DDRs ................................................................................. 40 • Changed Figure 6-7 and Figure 6-8 to include alternate SWB1_2 Timing .................................................. 42 • Changed SWB1_2 from: V3P3A to: V1P8U in Table 6-10 .................................................................... 42 • Changed VDDQ voltage to OTP Dependent and SWBx to SWB1_2 in Table 6-11 ....................................... 44 • Updated Figure 6-10 to include alternate SWB1_2 Timing .................................................................... 45 • Changed Section 6.4.5.5 to include alternate SWB1_2 Timing ............................................................... 46 • Changed Section 6.4.5.6 to include THERMTRIPB ........................................................................... 47 • Added the TPS65094x family OTP values to Section 6.7 ..................................................................... 52 • Replaced VID values with link to full VID table in Table 6-18 and Table 6-19 .............................................. 55 • Updated naming of bits in the TEMPHOT register .............................................................................. 70 |
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