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TPS65132T6YFFR Datasheet(PDF) 6 Page - Texas Instruments |
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TPS65132T6YFFR Datasheet(HTML) 6 Page - Texas Instruments |
6 / 64 page TPS65132 SLVSBM1G – JUNE 2013 – REVISED AUGUST 2015 www.ti.com Pin Functions PIN I/O DESCRIPTION NAME Ax, Bx, Lx Sx AGND D2 D2 — Analog ground CFLY1 C3 C3 I/O Negative charge pump flying capacitor pin CFLY2 A3 A3 I/O Negative charge pump flying capacitor pin EN — B1 Enable pin (sequence programmed) ENN A1 — I Enable pin for VNEG rail ENP B1 B1 I Enable pin for VPOS rail OUTP E3 E3 O Output pin of the LDO (VPOS) OUTN A2 A2 O Output pin of the negative charge pump (VNEG) B3 B3 PGND — Power ground E1 E1 D3 D3 REG I/O Boost converter output pin E2 E2 SCL B2 B2 I/O I²C interface clock signal pin SDA C2 C2 I/O I²C interface data signal pin SW D1 D1 I/O Switch pin of the boost converter SYNC — A1 I Synchronization pin. 150 mA current enabled if this pin is pulled HIGH. VIN C1 C1 I Input voltage supply pin 6 Submit Documentation Feedback Copyright © 2013–2015, Texas Instruments Incorporated Product Folder Links: TPS65132 |
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