TPS65138

TPS65138A

SLVSAV3C – APRIL 2011 – REVISED MAY 2012

www.ti.com

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERABLE PART

TOP-SIDE MARKING

RANGE

NUMBER

-2.2V ~ -6.2V

10-Pin 3x3 QFN

TPS65138DRCR

PUCC

-40°C to +85°

-2.2V ~ -5.2V

TPS65138ADRCR

PXJI

(1)

For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

website at www.ti.com.

(2)

Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

ABSOLUTE MAXIMUM RATINGS

(1)

over operating free-air temperature range (unless otherwise noted)

VALUE

UNIT

MIN

MAX

PVIN, SWP, OUTP, CTRL, VL

5.5

OUTN

–6.5

V

SWN

–6.5

4.8

CT

3.6

HBM

±2

kV

ESD rating

MM

±200

V

CDM

±500

V

–40

50

°C

–40

85

°C

–65

150

°C

(1)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating

conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2)

All voltage values are with respect to GND pin

THERMAL INFORMATION

(1)

DRC

THERMAL METRIC

UNITS

10-PINS

Junction-to-ambient thermal resistance

54.7

Junction-to-board thermal resistance

16.9

°C/W

Junction-to-top characterization parameter

4.2

Junction-to-board characterization parameter

19.5

(1)

For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953

2

Submit Documentation Feedback

Copyright © 2011–2012, Texas Instruments Incorporated

Product Folder Links: TPS65138 TPS65138A