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TPS650244 Datasheet(PDF) 10 Page - Texas Instruments |
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TPS650244 Datasheet(HTML) 10 Page - Texas Instruments |
10 / 33 page TPS650241-Q1, TPS650243-Q1, TPS650244-Q1 SLVS994A – SEPTEMBER 2009 – REVISED MARCH 2011 www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL I/O DESCRIPTION NAME NO. DEFDCDC3 32 I Input signal indicating VDCDC3 voltage. TPS650241: 0 = 0.9 V, 1 = 1.375 V TPS650243: 0 = 1.0 V, 1 = 1.2 V TPS650244: 0 = 1.55 V, 1 = 1.6 V EN_DCDC1 20 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator. EN_DCDC2 19 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator. EN_DCDC3 18 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator. LDO REGULATOR SECTION VINLDO 15 I Input voltage for LDO1 and LDO2 VLDO1 16 O Output voltage of LDO1 VLDO2 14 O Output voltage of LDO2 EN_LDO 17 I Enable input for LDO1 and LDO2. Logic high enables the LDOs, logic low disables the LDOs EN_Vdd_alive 24 I Enable input for Vdd_alive LDO. Logic high enables the LDO, logic low disables the LDO Vdd_alive 12 O Output voltage for Vdd_alive FB_LDO1 11 I Feedback pin for LDO1 FB_LDO2 10 I Feedback pin for LDO2 CONTROL AND I2C SECTION MODE 23 I Select between Power Safe Mode and forced PWM Mode for DCDC1, DCDC2 and DCDC3. In Power Safe Mode PFM is used at light loads, PWM for higher loads. If PIN is set to high level, forced PWM Mode is selected. If Pin has low level, then Device operates in Power Safe Mode. PWRFAIL 21 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition. PWRFAIL_SNS 30 I Input for the comparator driving the /PWRFAIL output 10 Submit Documentation Feedback Copyright © 2009–2011, Texas Instruments Incorporated Product Folder Link(s): TPS650241-Q1 TPS650243-Q1 TPS650244-Q1 |
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