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TPS70158 Datasheet(PDF) 11 Page - Texas Instruments |
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TPS70158 Datasheet(HTML) 11 Page - Texas Instruments |
11 / 42 page TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222I – DECEMBER 1999 – REVISED AUGUST 2010 Power-Good The PG1 is an open drain, active high output terminal that indicates the status of the VOUT1 regulator. When the VOUT1 reaches 95% of its regulated voltage, PG1 will go to a high impedance state. It will go to a low impedance state when it is pulled below 95% (for example, during an overload condition) of its regulated voltage. The open drain output of the PG1 terminal requires a pull-up resistor. Manual Reset Pins (MR1 and MR2) MR1 and MR2 are active low input terminals used to trigger a reset condition. When either MR1 or MR2 is pulled to logic low, a POR (RESET) will occur. These terminals have a 6mA pull-up current to VIN1. Sense (VSENSE1, VSENSE2) The sense terminals of fixed-output options must be connected to the regulator output, and the connection should be as short as possible. Internally, sense connects to high-impedance, wide-bandwidth amplifiers through a resistor-divider network and noise pickup feeds through to the regulator output. It is essential to route the sense connection in such a way to minimize or avoid noise pickup. Adding RC networks between the VSENSE terminals and VOUT terminals to filter noise is not recommended because these networks can cause the regulators to oscillate. FB1 and FB2 FB1 and FB2 are input terminals used for adjustable-output devices and must be connected to the external feedback resistor divider. FB1 and FB2 connections should be as short as possible. It is essential to route them in such a way as to minimize or avoid noise pickup. Adding RC networks between the FB terminals and VOUT terminals to filter noise is not recommended because these networks cause the regulators to oscillate. RESET Indicator The TPS701xx features a RESET (SVS, POR, or Power-On Reset). RESET can be used to drive power-on reset circuitry or a low-battery indicator. RESET is an active low, open drain output that indicates the status of the VOUT2 regulator and both manual reset pins (MR1 and MR2). When VOUT2 exceeds 95% of its regulated voltage, and MR1 and MR2 are in the high impedance state, RESET will go to a high-impedance state after 120ms delay. RESET will go to a low-impedance state when VOUT2 is pulled below 95% (for example, an overload condition) of its regulated voltage. To monitor VOUT1, the PG1 output pin can be connected to MR1 or MR2. The open drain output of the RESET terminal requires a pullup resistor. If RESET is not used, it can be left floating. VIN1 and VIN2 VIN1 and VIN2 are input to the regulators. Internal bias voltages are powered by VIN1. VOUT1 and VOUT2 VOUT1 and VOUT2 are output terminals of the LDO. Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 11 |
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