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SLB9660XT1.2 Datasheet(PDF) 9 Page - Infineon Technologies AG

No. de pieza SLB9660XT1.2
Descripción Electrónicos  Trusted Platform Module
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Fabricante Electrónico  INFINEON [Infineon Technologies AG]
Página de inicio  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

SLB9660XT1.2 Datasheet(HTML) 9 Page - Infineon Technologies AG

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Data Sheet
9
Revision 1.0 2014-12-12
SLB 9660 TPM1.2
Trusted Platform Module
Pin Description
Figure 4-2 Pinout of the SLB 9660VQ1.2 / SLB 9660XQ1.2 (PG-VQFN-32-13 Package, Top View)
Table 4-1 Buffer Types
Buffer Type
Description
TS
Tri-State pin
ST
Schmitt-Trigger pin
OD
Open-Drain pin
Table 4-2 I/O Signals
Pin Number
Name
Pin
Type
Buffer
Type
Function
PG-TSSOP-
28-2
PG-VQFN-
32-13
26
27
LAD0
I/O
TS
LPC Address/Data Bit 0
Multiplexed LPC command, address and data bus.
Connect these pins to the LAD[3:0] pins of the LPC
host.
23
24
LAD1
I/O
TS
LPC Address/Data Bit 1
see description of LAD0 above.
20
21
LAD2
I/O
TS
LPC Address/Data Bit 2
see description of LAD0 above.
17
19
LAD3
I/O
TS
LPC Address/Data Bit 3
see description of LAD0 above.
22
23
LFRAME# I
ST
LPC Framing Signal
LPC framing signal. This pin is connected to the
LPC LFRAME# signal and indicates the start of a
new cycle on the LPC bus or the termination of a
broken cycle. The signal is active low.
LAD1
TPM
SLB 9660VQ1.2
PG-VQFN-32-13
1
10
15
26
30
18
LFRAME#
LCLK
LAD2
VDD
LAD3
LRESET#
NC
22
7
VDD
GPIO
NC
NC
NC
NC
NC
NC


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