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TPS70151PWP Datasheet(PDF) 9 Page - Texas Instruments |
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TPS70151PWP Datasheet(HTML) 9 Page - Texas Instruments |
9 / 42 page NOTES: A. VRES is the minimum input voltage for a valid RESET. The symbol VRES is not currently listed within EIA or JEDEC standards for semiconductor symbology. VIN2 VRES (see Note A) VRES t t t VOUT2 Threshold Voltage RESET Output 120 ms Delay 120 ms Delay Output Undefined Output Undefined VIT+(see Note B) VIT− (see Note B) VIT+(see Note B) B. VIT −Trip voltage is typically 5% lower than the output voltage (95%VO) VIT− to VIT+ is the hysteresis voltage. VIT− (see Note B) NOTES: A. VPG1 is the minimum input voltage for a valid PG1. The symbol VPG1 is not currently listed within EIA or JEDEC standards for semiconductor symbology. VPG1 t t t Threshold Voltage PG1 Output Output Undefined Output Undefined VIT+ (see Note B) VIT+(see Note B) B. VIT −Trip voltage is typically 5% lower than the output voltage (95%VO) VIT− to VIT+ is the hysteresis voltage. VIN1 VOUT2 VPG1 (see Note A) VIT− (see Note B) VIT− (see Note B) VUVLO VUVLO TPS70145, TPS70148 TPS70151, TPS70158 TPS70102 www.ti.com SLVS222I – DECEMBER 1999 – REVISED AUGUST 2010 RESET Timing Diagram (with VIN1 Powered Up) PG1 Timing Diagram Copyright © 1999–2010, Texas Instruments Incorporated Submit Documentation Feedback 9 |
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