TPS701 datasheet(26/42 Pages) TI1

No. de pieza	TPS701

Descripción Electrónicos	Dual-Output Low Dropout Voltage Regulators with Power-Up Sequencing for Split-Voltage DSP Systems

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Fabricante Electrónico	TI1 [Texas Instruments]

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26 / 42 page

RESET

VOUT2

VIN1

VIN2

EN

SEQ

VOUT1

VSENSE1

PG1

MR2

RESET

MR1

VSENSE2

VOUT2

VI

VOUT1

MR1

0.1

µF

10

µF

10

µF

0.1

µF

MR2

EN

TPS701xxPWP

(Fixed Output Option)

>2 V

<0.7 V

250 k

Ω

120ms

EN

VOUT2

VOUT1

PG1

MR1

MR2

(MR2 tied to PG1)

RESET

SEQUENCE

95%

83%

95%

NOTE A: t1 − Time at which both VOUT1 and VOUT2 are greater than the PG1 thresholds and MR1 is logic high.

t1

(see Note A)

VOUT1 faults out

TPS70145, TPS70148

TPS70151, TPS70158

TPS70102

SLVS222I – DECEMBER 1999 – REVISED AUGUST 2010

www.ti.com

Application condition: MR2 is tied to PG1, VIN1 and

VIN2 are tied to the same input voltage, the SEQ pin

is tied to logic high and VOUT1 faults out.

VOUT2 begins to power up when the device is enabled

(EN is pulled low). When VOUT2 reaches 83% of its

regulated voltage, then VOUT1 begins to power up.

When VOUT1 reaches 95% of its regulated voltage,

PG1 turns on and RESET switches to high voltage

level after a 120ms delay. When VOUT1 faults out,

VOUT2 remains powered on because the SEQ pin is

high. PG1 is tied to MR2 and both change state to

logic low. RESET is driven by MR2 and goes to logic

low when VOUT1 faults out (see Figure 43).

Figure 43. Timing when VOUT1 Faults Out

26

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