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TPS92602QPWPRQ1 Datasheet(PDF) 6 Page - Texas Instruments |
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TPS92602QPWPRQ1 Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 47 page  TPS92601-Q1, TPS92602-Q1, TPS92601A-Q1, TPS92602A-Q1 SLUSBP5D – MARCH 2014 – REVISED JANUARY 2015 www.ti.com Electrical Characteristics (continued) TJ = –40°C to 150°C, VVDD = 12 VDC, over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GATE DRIVER SUPPLY VCC V(VCC) Output voltage VIN > 6 V 5.5 6.6 7.4 V V(VCC_dr) Drop-out voltage 4 V < VIN < 8 V, I(VCC) < 50 mA 400 mV C(VCC) VCC buffer capacitance 2.2 10 20 µF I(VCC) Output current (only for internal usage) 80 mA I(VCC_LIM) Current limit VCC shorted to ground 150 220 mA GATE DRIVER – LOW-SIDE BOOST NMOS-FET Gate-source voltage to switch on boost NMOS VGS(NMOS) NMOS gate-source voltage 5.5 6.6 7.4 V FET. Depends on VCC D(MAX) Maximum duty cycle 93.8% tr(NMOS) Gate driver rising VCC = 6.6 V, no load 22 ns tf(NMOS) Gate driver falling VCC = 6 V, no load 8.5 ns rDS(on)(Source,Nmos) Gate driver resistance, sourcing VCC = 6.6 V, 100-mA load 2.5 4 Ω rDS(on)(Sink,Nmos) Gate driver resistance, sinking VCC = 6.6 V, 100-mA load 2.5 4 Ω CURRENT LIMIT – NMOS FET Voltage limit threshold across sense- V(ISNSx) 83 100 115 mV current resistor t(ISNSx) Leading edge blanking 200 ns I(ISNSx) Current on ISNSx 40 50 65 µA A(PS) VC current-mode gain ( ΔVvc / ΔVsns) 4 V/V GATE DRIVER – HIGH-SIDE PWM PMOS-FET I(PWMOx_Source) Peak source current V(OUT) – V(PWMOx) = 6.5 V, V(OUT) = 40 V 150 mA I(PWMOx_Sink) Peak sink current V(OUT) – V(PWMOx) = 0 V, V(OUT) = 40 V 10 mA V(PWMOx) Output voltage 4 75 V VGS(PMOS) PMOS gate-source voltage PWMx = high, V(OUT) = 40 V 6 6.9 8 V Sufficient gate-source voltage to switch on the VGS(NMOS) NMOS gate-source voltage 5.5 6.6 7.4 V NMOS FET; this depends on VCC. tr(PMOS) HS gate driver rising No load 1 µs tf(PMOS) HS gate driver falling No load 3 µs PWM DIMMING f(PWMIN) Dimming frequency See PWM dimming section 0.2 2 kHz V(thLOW) Logic low Switch off PMOS dimming FET (low below) 0.8 V V(thHIGH) Logic high Switch on PMOS dimming FET (high above) 2 V R(PWMIN_pd) Pulldown resistance at PWMINx pin 90 120 150 k Ω PWMIN to LED turnoff time 80 ns PWMIN to LED turnon time 60 ns INTERNAL PLL OSCILLATOR f(OSC) Oscillator range 100 600 kHz RT: 20-k Ω resistor. See Equation 2 and Figure 3 Δf(OSC) Oscillator accuracy –20% 20% for f(OSC) vs RT f(EXT) Ext. synchronization 100 600 kHz t(CLKpw) Minimum clock input pulse duration 70 ns V(RTthLO) RT low voltage 0.8 V V(RTthHI) RT high voltage 2 V t(RTdelay) RT rising edge to GDRV1 rising edge 35 ns t(PLLlock) PLL lock-in time 200 µs 6 Submit Documentation Feedback Copyright © 2014–2015, Texas Instruments Incorporated Product Folder Links: TPS92601-Q1 TPS92602-Q1 TPS92601A-Q1 TPS92602A-Q1 |
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