LC75806PT

No.A1425-2/35

Specifications

Absolute Maximum Ratings

at Ta = 25

°C, VSS = 0V

Parameter

Symbol

Conditions

Ratings

Unit

Maximum supply voltage

VDD max

VDD

-0.3 to +7.0

V

VIN1

CE, CL, DI, RES

-0.3 to +7.0

Input voltage

VIN2

OSC, TEST, VDD1, VDD2, KI1 to KI5

-0.3 to VDD+0.3

V

VOUT1

DO

-0.3 to +7.0

Output voltage

VOUT2

OSC, S1 to S77, COM1 to COM4, KS1 to KS6, P1 to P9

-0.3 to VDD+0.3

V

IOUT1

S1 to S77

300

μA

IOUT2

COM1 to COM4

3

IOUT3

KS1 to KS6

1

Output current

IOUT4

P1 to P9

5

mA

Allowable power dissipation

Pd max

Ta=85

°C

200

mW

Operating temperature

Topr

-40 to +85

°C

Storage temperature

Tstg

-55 to +125

°C

Allowable Operating Ranges

at Ta = -40 to +85

°C, VSS = 0V

Ratings

Parameter

Symbol

Conditions

min

typ

max

Unit

Supply voltage

VDD

VDD

4.5

6.0

V

VDD1

VDD1

2/3VDD0

VDD0

Input voltage

*1

VDD2

VDD2

1/3VDD0

VDD0

V

VIH1

CE, CL, DI, RES

0.4VDD

6.0

VIH2

KI1 to KI5

0.6VDD

VDD

Input high level voltage

VIH3

OSC: External clock operating mode

0.4VDD

VDD

V

VIL1

CE, CL, DI, RES

0

0.2VDD

VIL2

KI1 to KI5

0

0.2VDD

Input low level voltage

VIL3

OSC: External clock operating mode

0

0.2VDD

V

Recommended external

resistor for RC oscillation

ROSC

OSC: RC oscillation operating mode

39

k

Ω

Recommended external

capacitor for RC oscillation

COSC

OSC: RC oscillation operating mode

1000

pF

Guaranteed range of RC oscillation

fOSC

OSC: RC oscillation operating mode

19

38

76

kHz

External clock operating frequency

fCK

OSC: External clock operating mode

[Figure4]

10

38

76

kHz

External clock duty cycle

DCK

OSC: External clock operating mode

[Figure4]

30

50

70

%

Data setup time

tds

CL, DI

[Figure2], [Figure3]

160

ns

Data hold time

tdh

CL, DI

[Figure2], [Figure3]

160

ns

CE wait time

tcp

CE, CL

[Figure2], [Figure3]

160

ns

CE setup time

tcs

CE, CL

[Figure2], [Figure3]

160

ns

CE hold time

tch

CE, CL

[Figure2], [Figure3]

160

ns

High level clock pulse width

tφH

CL

[Figure2], [Figure3]

160

ns

Low level clock pulse width

tφL

CL

[Figure2], [Figure3]

160

ns

Rise time

tr

CE, CL, DI

[Figure2], [Figure3]

160

ns

Fall time

tf

CE, CL, DI

[Figure2], [Figure3]

160

ns

DO output deley time

tdc

DO RPU=4.7kΩ CL=10pF *2

[Figure2], [Figure3]

1.5

μs

DO rise time

tdr

DO RPU=4.7kΩ CL=10pF *2

[Figure2], [Figure3]

1.5

μs

Note:

*

1. VDD0=0.70VDD to VDD

*

2. Since the DO pin is an open-drain output, these times depend on the values of the pull-up resistorRPU and the load

capacitance CL.

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating

Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.