Motor de Búsqueda de Datasheet de Componentes Electrónicos
  Spanish  ▼
ALLDATASHEET.ES

X  

TSB41LV06A Datasheet(PDF) 8 Page - Texas Instruments

No. de pieza TSB41LV06A
Descripción Electrónicos  IEEE 1394b SIX-PORT CABLE TRANSCEIVER/ARBITER
Download  52 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

TSB41LV06A Datasheet(HTML) 8 Page - Texas Instruments

Back Button TSB41LV06A_16 Datasheet HTML 4Page - Texas Instruments TSB41LV06A_16 Datasheet HTML 5Page - Texas Instruments TSB41LV06A_16 Datasheet HTML 6Page - Texas Instruments TSB41LV06A_16 Datasheet HTML 7Page - Texas Instruments TSB41LV06A_16 Datasheet HTML 8Page - Texas Instruments TSB41LV06A_16 Datasheet HTML 9Page - Texas Instruments TSB41LV06A_16 Datasheet HTML 10Page - Texas Instruments TSB41LV06A_16 Datasheet HTML 11Page - Texas Instruments TSB41LV06A_16 Datasheet HTML 12Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 8 / 52 page
background image
TSB41LV06A
IEEE 1394a SIXPORT CABLE TRANSCEIVER/ARBITER
SLLS363A − SEPTEMBER 1999 − REVISED NOVEMBER 2000
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
TYPE
I/O
DESCRIPTION
NAME
NO.
TYPE
I/O
DESCRIPTION
LPS
24
CMOS
5 V tol
I
Link power status input. This terminal is used to monitor the active/power status of the link layer
controller and to control the state of the PHY-LLC interface. This terminal should be connected to
either the VDD supplying the LLC through a 10 kΩ resistor, or to a pulsed output which is active when
the LLC is powered. A pulsed signal should be used when an isolation barrier exists between the
LLC and PHY (see Figure 8).
The LPS input is considered inactive if it is sampled low by the PHY for more than 2.6
µs (128
SYSCLK cycles), and is considered active otherwise (i.e., asserted steady high or an oscillating
signal with a low time less than 2.6
µs). The LPS input must be high for at least 21 ns in order to be
guaranteed to be observed as high by the PHY.
When the TSB41LV06A detects that LPS is inactive, it places the PHY-LLC interface into a
low-power reset state. In the reset state, the CTL and D outputs are held in the logic zero state and
the LREQ input is ignored; however, the SYSCLK output remains active. If the LPS input remains
low for more than 26
µs (1280 SYSCLK cycles), the PHY-LLC interface is put into a low-power
disabled state in which the SYSCLK output is also held inactive. The PHY-LLC interface is placed
into the disabled state upon hardware reset.
The LLC is considered active only if both the LPS input is active and the LCtrl register bit is set to 1,
and is considered inactive if either the LPS input is inactive or the the LCtrl register bit is cleared to 0.
LREQ
3
CMOS
5 V tol
I
LLC request input. The LLC uses this input to initiate a service request to the TSB41LV06A. Bus
holder is built into this terminal.
PC0
PC1
PC2
28
29
30
CMOS
I
Power class programming inputs. On hardware reset, these inputs set the default value of the
power-class indicated during self-ID. Programmed is done by tying the terminals high or low. Refer
to Table 9 for encoding.
PD
23
CMOS
5 V tol
I
Power-down input. A high on this terminal turns off all internal circuitry except the cable-active
monitor circuits, which control the CNA output. Asserting the PD input high also activates an internal
pulldown on the RESET terminal so as to force a reset of the internal control logic
PLLGND
94, 95
Supply
PLL circuit ground terminals. These terminals should be tied together to the low impedance circuit
board ground plane.
PLLVDD
93
Supply
PLL circuit power terminals. A combination of high frequency decoupling capacitors near each
terminal are suggested, such as paralleled 0.1
µF and 0.001 µF. Lower frequency 10-µF filtering
capacitors are also recommended. These supply terminals are separated from DVDD and AVDD
internal to the device to provide noise isolation. They should be tied at a low impedance point on the
circuit board.
SE
42
CMOS
I
Test control input. This input is used in manufacturing test of the TSB41LV06A. For normal use this
terminal should be tied to GND through a 1-k
Ω pulldown resistor.
SM
43
CMOS
I
Test control input. This input is used in manufacturing test of the TSB41LV06A. For normal use this
terminal should be tied to GND.
SYSCLK
5
CMOS
O
System clock output. Provides a 49.152 MHz clock signal, synchronized with data transfers, to the
LLC.
TESTM
41
CMOS
I
Test control input. This input is used in manufacturing test of the TSB41LV06A. For normal use this
terminal should be tied to VDD.
TPA0+
TPA1+
TPA2+
TPA3+
TPA4+
TPA5+
39
55
61
67
73
88
Cable
I/O
Twisted-pair cable A differential signal terminals. Board traces from each pair of positive and
negative differential signal terminals should be kept matched and as short as possible to the
TPA0−
TPA1−
TPA2−
TPA3−
TPA4−
TPA5−
38
54
60
66
72
87
Cable
I/O
negative differential signal terminals should be kept matched and as short as possible to the
external load resistors and to the cable connector. For an unused port,TPA+ and TPA−can be left
open.


Número de pieza similar - TSB41LV06A_16

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Texas Instruments
TSB41LV06APZP TI-TSB41LV06APZP Datasheet
617Kb / 48P
[Old version datasheet]   IEEE 1394a SIX-PORT CABLE TRANSCEIVER/ARBITER
More results

Descripción similar - TSB41LV06A_16

Fabricante ElectrónicoNo. de piezaDatasheetDescripción Electrónicos
logo
Texas Instruments
TSB81BA3IPFPEP TI1-TSB81BA3IPFPEP Datasheet
711Kb / 57P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3B TI-TSB41BA3B Datasheet
1Mb / 67P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB81BA3 TI-TSB81BA3 Datasheet
810Kb / 57P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3A TI1-TSB41BA3A_16 Datasheet
222Kb / 11P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3D TI-TSB41BA3D Datasheet
875Kb / 59P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3D TI1-TSB41BA3D_14 Datasheet
754Kb / 60P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3A-EP TI1-TSB41BA3A-EP_14 Datasheet
768Kb / 69P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB41BA3B-EP TI1-TSB41BA3B-EP Datasheet
1,023Kb / 67P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER  
TSB81BA3D TI1-TSB81BA3D_12 Datasheet
682Kb / 61P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
TSB81BA3E TI-TSB81BA3E Datasheet
887Kb / 57P
[Old version datasheet]   IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER
More results


Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52


Datasheet Descarga

Go To PDF Page


Enlace URL




Política de Privacidad
ALLDATASHEET.ES
¿ALLDATASHEET es útil para Ud.?  [ DONATE ] 

Todo acerca de Alldatasheet   |   Publicidad   |   Contáctenos   |   Política de Privacidad   |   Intercambio de Enlaces   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com