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MSC1200 Datasheet(PDF) 27 Page - Texas Instruments |
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MSC1200 Datasheet(HTML) 27 Page - Texas Instruments |
27 / 60 page MSC1200 27 SBAS289E www.ti.com Serial Flash Programming Mode Two methods of programming are available: serial program- ming mode and user application mode. Serial programming mode is initiated by holding the P1.0/PROG pin low during POR, as shown in Figure 21. User Application mode also allows for Flash programming. Code execution from Flash Memory cannot occur in this mode while programming, but code execution can occur from Boot ROM while programming. INTERRUPT INTERRUPT/EVENT ADDR NUM PRIORITY FLAG ENABLE CONTROL HIGH AVDD Low Voltage Detect 33H 6 0 ALVDIP (AIPOL.1)(1) EALV (AIE.1)(1) N/A Count (SPI / I2C) 33H 6 0 CNTIP (AIPOL.2)(1) ECNT (AIE.2)(1) N/A I2C Start/Stop 33H 6 0 I2CIP (AIPOL.3)(1) EI2C (AIE.3)(1) N/A Milliseconds Timer 33H 6 0 MSECIP (AAIPOLIE.4)(1) EMSEC (AIE.4)(1) N/A ADC 33H 6 0 ADCIP (AIPOL.5)(1) EADC (AIE .5)(1) N/A Summation Register 33H 6 0 SUMIP (AIPOL.6)(1) ESUM (AIE.6)(1) N/A Seconds Timer 33H 6 0 SECIP (AIPOL.7)(1) ESEC (AIE.7)(1) N/A External Interrupt 0 03H 0 1 IE0 (TCON.1)(2) EX0 (IE.0)(4) PX0 (IP.0) Timer 0 Overflow 0BH 1 2 TF0 (TCON.5)(3) ET0 (IE.1)(4) PT0 (IP.1) External Interrupt 1 13H 2 3 IE1 (TCON.3)(2) EX1 (IE.2)(4) PX1 (IP.2) Timer 1 Overflow 1BH 3 4 TF1 (TCON.7)(3) ET1 (IE.3)(4) PT1 (IP.3) Serial Port 0 23H 4 5 RI_0 (SCON0.0) ES0 (IE.4)(4) PS0 (IP.4) TI_0 (SCON0.1) External Interrupt 2 43H 8 6 IE2 (EXIF.4) EX2 (EIE.0)(4) PX2 (EIP.0) External Interrupt 3 4BH 9 7 IE3 (EXIF.5) EX3 (EIE.1)(4) PX3 (EIP.1) External Interrupt 4 53H 10 8 IE4 (EXIF.6) EX4 (EIE.2)(4) PX4 (EIP.2) External Interrupt 5 5BH 11 9 IE5 (EXIF.7) EX5 (EIE.3)(4) PX5 (EIP.3) Watchdog 63H 12 10 WDTI (EICON.3) EWDI (EIE.4)(4) PWDI (EIP.4) LOW NOTES: (1) These interrupts set the AI flag (EICON.4) and are enabled by EAI (EICON.5). (2) If edge triggered, cleared automatically by hardware when the service routine is vectored to. If level triggered, the flag follows the state of the pin. (3) Cleared automatically by hardware when interrupt vector occurs. (4) Globally enabled by EA (IE.7). TABLE VII. Interrupt Summary. INTERRUPT INTERRUPTS The MSC1200 uses a three-priority interrupt system. As shown in Table VII, each interrupt source has an indepen- dent priority bit, flag, interrupt vector, and enable (except that nine interrupts share the Auxiliary Interrupt (AI) at the highest priority). In addition, interrupts can be globally enabled or disabled. The interrupt structure is compatible with the origi- nal 8051 family. All of the standard interrupts are available. HARDWARE CONFIGURATION MEMORY The 64 configuration bytes can only be written during the program mode. The bytes are accessed through SFR regis- ters CADDR (SFR 93H) and CDATA (SFR 94H). Three of the configuration bytes control Flash partitioning and system control. If the security bit is set, these bits cannot be changed except with a Mass Erase command that erases all of the Flash Memory including the 64 configuration bytes. FIGURE 21. Serial Programming Mode. MSC1200 Programmer P3.0/RxD0 P3.1/TxD0 P1.0/PROG NOTE: For user application mode, avoid heavy loading on P1.0/PROG, which may result in erroneously entering serial programming mode on power-up. |
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