74HC257N datasheet(2/13 Pages) PHILIPS

No. de pieza	74HC257N

Descripción Electrónicos	Quad 2-input multiplexer 3-state

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Fabricante Electrónico	PHILIPS [NXP Semiconductors]

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1998 Sep 30

2

Philips Semiconductors

Product speciﬁcation

Quad 2-input multiplexer; 3-state

74HC/HCT257

FEATURES

• Non-inverting data path

• 3-state outputs interface directly with system bus

• Output capability: bus driver

• ICC category: MSI

GENERAL DESCRIPTION

The 74HC/HCT257 are high-speed Si-gate CMOS devices

and are pin compatible with low power Schottky TTL

(LSTTL). They are specified in compliance with JEDEC

standard no. 7A.

The 74HC/HCT257 have four identical 2-input multiplexers

with 3-state outputs, which select 4 bits of data from two

sources and are controlled by a common data select

input (S).

The data inputs from source 0 (1I0 to 4I0) are selected

when input S is LOW and the data inputs from source 1

(1I1 to 4I1) are selected when S is HIGH. Data appears at

the outputs (1Y to 4Y) in true (non-inverting) form from the

selected inputs.

The “257” is the logic implementation of a 4-pole,

2-position switch, where the position of the switch is

determined by the logic levels applied to S. The outputs

are forced to a high impedance OFF-state when OE is

HIGH.

The logic equations for the outputs are:

1Y = OE.(1I1.S + 1I0.S)

2Y = OE.(2I1.S + 2I0.S)

3Y = OE.(3I1.S + 3I0.S)

4Y = OE.(4I1.S + 4I0.S)

The “257” is identical to the “258” but has non-inverting

(true) outputs.

QUICK REFERENCE DATA

GND = 0 V; Tamb =25 °C; tr =tf = 6 ns

Notes

1. CPD is used to determine the dynamic power dissipation (PD in µW):

PD =CPD × VCC2 × fi +∑ (CL × VCC2 × fo) where:

fi = input frequency in MHz

fo = output frequency in MHz

∑ (CL × VCC2 × fo) = sum of outputs

CL = output load capacitance in pF

VCC = supply voltage in V

2. For HC the condition is VI = GND to VCC

For HCT the condition is VI = GND to VCC − 1.5 V

SYMBOL

PARAMETER

CONDITIONS

TYPICAL

UNIT

HC

HCT

tPHL/ tPLH

propagation delay

CL = 15 pF; VCC =5 V

nI0, nI1 to nY

11

13

ns

S to nY

14

17

ns

CI

input capacitance

3.5

pF

CPD

power dissipation capacitance per multiplexer

notes 1 and 2

45

pF

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