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MC100EP16VBDTG Datasheet(PDF) 6 Page - ON Semiconductor |
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MC100EP16VBDTG Datasheet(HTML) 6 Page - ON Semiconductor |
6 / 8 page MC100EP16VB www.onsemi.com 6 0 100 200 300 400 500 600 700 800 900 0 500 1000 1500 2000 2500 3000 3500 4000 Figure 3. Fmax/Jitter for Q Output FREQUENCY (MHz) 1 2 3 4 5 6 7 8 9 Figure 4. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D − Termination of ECL Logic Devices) Driver Device Receiver Device QD Q D Zo = 50 W Zo = 50 W 50 W 50 W VTT VTT = VCC − 2.0 V Resource Reference of Application Notes AN1405/D − ECL Clock Distribution Techniques AN1406/D − Designing with PECL (ECL at +5.0 V) AN1503/D − ECLinPSt I/O SPiCE Modeling Kit AN1504/D − Metastability and the ECLinPS Family AN1568/D − Interfacing Between LVDS and ECL AN1672/D − The ECL Translator Guide AND8001/D − Odd Number Counters Design AND8002/D − Marking and Date Codes AND8020/D − Termination of ECL Logic Devices AND8066/D − Interfacing with ECLinPS AND8090/D − AC Characteristics of ECL Devices |
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