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BUSY Datasheet(PDF) 6 Page - Xilinx, Inc

No. de Pieza. BUSY
Descripción  Defense Grade Platform Flash In-System Programmable Configuration PROM
Descarga  27 Pages
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Fabricante  XILINX [Xilinx, Inc]
Página de inicio  http://www.xilinx.com
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BUSY Datasheet(HTML) 6 Page - Xilinx, Inc

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Defense Grade Platform Flash In-System Programmable Configuration PROM
DS541 (v3.0) August 5, 2015
www.xilinx.com
Product Specification
6
—PRODUCT OBSOLETE / UNDER OBSOLESCENCE—
USERCODE Register
The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information
about the device's programmed contents. By using the USERCODE instruction, a user-programmable identification code
can be shifted out for examination. This code is loaded into the USERCODE register during programming of the Platform
Flash PROM. If the device is blank or was not loaded during programming, the USERCODE register contains FFFFFFFFh.
Customer Code Register
For the XQF32P Platform Flash PROM, in addition to the USERCODE, a unique 32-byte Customer Code can be assigned
to each design revision enabled for the PROM. The Customer Code is set during programming, and is typically used to
supply information about the design revision contents. A private JTAG instruction is required to read the Customer Code. If
the PROM is blank, or the Customer Code for the selected design revision was not loaded during programming, or if the
particular design revision is erased, the Customer Code contains all ones.
Platform Flash PROM TAP Characteristics
The Platform Flash PROM family performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via
a single 4-wire test access port (TAP). This simplifies system designs and allows standard automatic test equipment (ATE)
to perform both functions. The AC characteristics of the Platform Flash PROM TAP are described as follows.
TAP Timing
Figure 3 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both
boundary-scan and ISP operations.
TAP AC Parameters
Table 5 shows the timing parameters for the TAP waveforms shown in Figure 3.
X-Ref Target - Figure 3
Figure 3: Test Access Port Timing
Table 5: Test Access Port Timing Parameters
Symbol
Description
Min
Max
Units
TCKMIN
TCK minimum clock period when VCCJ = 2.5V or 3.3V
100
ns
TMSS
TMS setup time when VCCJ = 2.5V or 3.3V
10
ns
TMSH
TMS hold time when VCCJ = 2.5V or 3.3V
25
ns
TDIS
TDI setup time when VCCJ = 2.5V or 3.3V
10
ns
TDIH
TDI hold time when VCCJ = 2.5V or 3.3V
25
ns
TDOV
TDO valid delay when VCCJ = 2.5V or 3.3V
30
ns
TCK
TCKMIN
TMSS
TMS
TDI
TDO
TMSH
TDIH
TDOV
TDIS
DS541_03_111706
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