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NB4L6254MNG Datasheet(PDF) 1 Page - ON Semiconductor

No. de Pieza. NB4L6254MNG
Descripción  2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
Descarga  11 Pages
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Fabricante  ONSEMI [ON Semiconductor]
Página de inicio  http://www.onsemi.com
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NB4L6254MNG Datasheet(HTML) 1 Page - ON Semiconductor

 
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© Semiconductor Components Industries, LLC, 2009
March, 2009 − Rev. 3
1
Publication Order Number:
NB4L6254/D
NB4L6254
2.5V / 3.3V Differential
LVPECL 2x2 Clock Switch
and Low Skew Fanout
Buffer
Description
The NB4L6254 is a differential 2x2 clock switch and drives
precisely aligned clock signals through its LVPECL fanout buffers. It
employs a fully differential architecture with bipolar technology,
offers superior digital signal characteristics, has very low clock output
skew and supports clock frequencies from DC up to 3.0 GHz.
The NB4L6254 is designed for the most demanding, skew critical
differential clock distribution systems. Typical applications for the
NB4L6254 are clock distribution, switching and data loopback
systems of high−performance computer, networking and
telecommunication systems, as well as on−board clocking of OC−3,
OC−12 and OC−48 communication systems. In addition, the
NB4L6254 can be configured as a single 1:6 or dual 1:3 LVPECL
fanout buffer.
The NB4L6254 can be operated from a single 3.3 V or 2.5 V power
supply.
Features
Maximum Clock Input Frequency, 3 GHz
Maximum Input Data Rate, 3 Gb/s
Differential LVPECL Inputs and Outputs
Low Output Skew: 50 ps Maximum Output−to−Output Skew
Synchronous Output Enable Eliminating Output Runt Pulse
Generation and Metastability
Operating Range: Single 3.3 V or 2.5 V Supply
VCC = 2.375 V to 3.465 V
LVCMOS Compatible Control Inputs
Packaged in LQFP−32
Fully Differential Architecture
−40°C to 85°C Ambient Operating Temperature
These are Pb−Free Devices*
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
LQFP−32
FA SUFFIX
CASE 873A
MARKING DIAGRAMS*
http://onsemi.com
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
A
= Assembly Location
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G or G = Pb−Free Package
(Note: Microdot may be in either location)
NB4L
6254
AWLYYWWG
32
1
NB4L6254
AWLYYWWG
G
1
QFN32
MN SUFFIX
CASE 488AM
OEA
QA0
QA0
QA1
QA1
QA2
QA2
QB0
QB0
QB1
QB1
QB2
QB2
0
1
0
1
Bank A
Bank B
OEB
SEL0
SEL1
CLK1
CLK1
CLK0
CLK0
VCC
VCC
Figure 1. Functional Block Diagram
SYNC


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