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BCM3814B60E15A3C02 Datasheet(PDF) 11 Page - Vicor Corporation |
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BCM3814B60E15A3C02 Datasheet(HTML) 11 Page - Vicor Corporation |
11 / 39 page BCM® in a VIA Package Rev 1.4 vicorpower.com Page 11 of 39 09/2016 800 927.9474 BCM3814x60E15A3yzz SCL SDA S SP P V IH V IL V IH V IL t BUF t HD,STA t LOW t R t HD,DAT t HIGH t F t SU,DAT t SU,STA t SU,STO Serial Clock input (SCL) AND Serial Data (SDA) Pins • Highηpower SMBus specification and SMBus physical layer compatible. Note that optional SMBALERT# is signal not supported. • PMBusTM command compatible. • The internal µC requires the use of a flipηflop to drive SSTOP. See system diagram section for more details. SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT DIGITAL INPUT/OUTPUT Regular Operation Electrical Parameters Input Voltage Threshold VIH VVDD_IN = 3.3V 2.1 V VIL VVDD_IN = 3.3V 0.8 V Output Voltage Threshold VOH VVDD_IN = 3.3V 3 V VOL VVDD_IN = 3.3V 0.4 V Leakage current ILEAKηPIN Unpowered device 10 µA Signal Sink Current ILOAD VOL = 0.4V 4 mA Signal Capacitive Load CI Total capacitive load of one device pin 10 pF Signal Noise Immunity VNOISE_PP 10MHz to 100MHz 300 mV Timing Parameters Operating Frequency FSMB Idle state = 0Hz 10 400 KHz Free time between Stop and Start Condition tBUF 1.3 µs Hold time after Start or Repeated Start condition tHD:STA First clock is generated after this hold time 0.6 µs Repeat Start Condition Setup time tSU:STA 0.6 µs Stop Condition setup time tSU:STO 0.6 µs Data Hold time tHD:DAT 300 ns Data Setup time tSU:DAT 100 ns Clock low time out tTIMEOUT 25 35 ms Clock low period tLOW 1.3 µs Clock high period tHIGH 0.6 50 µs Cumulative clock low extend time tLOW:SEXT 25 ms Clock or Data Fall time tF Measured from (VIL_MAX η 0.15) to (VIH_MIN + 0.15) 20 300 ns Clock or Data Rise time tR 0.9 • VVDD_IN_MAX to (VIL_MAX η 0.15) 20 300 ns |
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