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TPS3850H01DRCT Datasheet(PDF) 3 Page - Texas Instruments |
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TPS3850H01DRCT Datasheet(HTML) 3 Page - Texas Instruments |
3 / 44 page 1 VDD 10 SENSE 2 CWD 9 RESET 3 SET0 8 WDO 4 CRST 7 WDI 5 GND 6 SET1 Not to scale Thermal Pad 3 TPS3850 www.ti.com SBVS301A – OCTOBER 2016 – REVISED NOVEMBER 2016 Product Folder Links: TPS3850 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated 5 Pin Configuration and Functions DRC Package: TPS3850 3-mm × 3-mm VSON-10 Top View Pin Functions PIN DESCRIPTION NAME NO. I/O CRST 4 I Programmable reset timeout pin. Connect a capacitor between this pin and GND to program the reset timeout period. This pin can also be connected by a 10-kΩ pullup resistor to VDD, or left unconnected (NC) for various factory programmed reset timeout options; see the CRST Delay section. When using an external capacitor, use Equation 3 to determine the reset timeout. CWD 2 I Programmable watchdog timeout input. Watchdog timeout is set by connecting a capacitor between this pin and ground. Furthermore, this pin can also be connected by a 10-kΩ resistor to VDD, or leaving unconnected (NC) further enables the selection of the preset watchdog timeouts; see the Timing Requirements table. When using a capacitor, the TPS3850 determines the window watchdog upper boundary with Equation 6. The lower watchdog boundary is set by the SET pins, see Table 6 and the CWD Functionality section for additional information. GND 5 — Ground pin RESET 9 O Reset output. Connect RESET using a 1-kΩ to 100-kΩ resistor to VDD. RESET goes low when the voltage at the SENSE pin goes below the undervoltage threshold (VIT-(UV)) or above the overvoltage threshold (VIT+(OV)). When the voltage level at the SENSE pin is within the normal operating range, the RESET timeout counter starts. At timer completion, RESET goes high. During startup, the state of RESET is undefined below the specified power-on reset voltage (VPOR). Above VPOR, RESET goes low and remains low until the monitored voltage is within the correct operating range (between VIT-(UV) and VIT(+OV)) and the RESET timeout is complete. SENSE 10 I SENSE input to monitor voltage rail. Connect this pin to the supply rail that must be monitored. SET0 3 I Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog; see the Timing Requirements table. SET1 6 I Logic input. SET0, SET1, and CWD select the watchdog window ratios, timeouts, and disable the watchdog; see the Timing Requirements table. VDD 1 I Supply voltage pin. For noisy systems, connecting a 0.1-µF bypass capacitor is recommended. WDI 7 I Watchdog input. A falling transition (edge) must occur at this pin between the lower (tWDL(max)) and upper (tWDU(min)) window boundaries in order for WDO to not assert. When the watchdog is not in use, the SET pins can be used to disable the watchdog. The input at WDI is ignored when RESET or WDO are low (asserted) and also when the watchdog is disabled. If the watchdog is disabled, then WDI cannot be left unconnected and must be driven to either VDD or GND. WDO 8 O Watchdog output. Connect WDO with a 1-kΩ to 100-kΩ resistor to VDD. WDO goes low (asserts) when a watchdog timeout occurs. WDO only asserts when RESET is high. When a watchdog timeout occurs, WDO goes low (asserts) for the set RESET timeout delay (tRST). When RESET goes low, WDO is in a high-impedance state. Thermal pad — Connect the thermal pad to a large-area ground plane. The thermal pad is internally connected to GND. |
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