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BU1S12S1AG-LB Datasheet(PDF) 10 Page - Rohm

No. de pieza BU1S12S1AG-LB
Descripción Electrónicos  Successive Approximation A/D Converter
Download  20 Pages
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Fabricante Electrónico  ROHM [Rohm]
Página de inicio  http://www.rohm.com
Logo ROHM - Rohm

BU1S12S1AG-LB Datasheet(HTML) 10 Page - Rohm

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BU1S12S1AG-LB
10/16
© 2016 ROHM Co., Ltd. All rights reserved.
www.rohm.com
TSZ22111・15・001
TSZ02201-0GSG0GZ10180-1-2
04.Jul.2016 Rev.001
3. Serial Interface
The serial interface timing is shown in Figure 21. When CSB goes low, both a conversion process and data transfer are
started. At the falling edge of CSB, SDATA changes its state from High-Z to Low, the converter moves from Track mode
to Hold mode. A tracked input signal is sampled and held for conversion at this point. The converter returns from Hold
mode back to Track mode at the rising edge of SCLK subsequent to the 13th falling edge of it. SDATA goes back to
High-Z at the 16th falling edge of SCLK or at the rising edge of CSB. After a conversion, the quiet time tQUIET must be
satisfied before the next conversion triggered by the falling edge of CSB.
Sixteen SCLK cycles are needed to read a complete data of the A/D conversion from BU1S12S1AG-LB. First, four
leading zeros come out from SDATA. Then, the 12bit data comes out bit by bit, starting from the MSB. The first zero is
clocked out at the falling edge of CSB. The remaining leading 3 zeros and data bits are clocked out to SDATA at the
falling edge of SCLK; the host IC, the receiver of the A/D conversion data, is intended to receive the data at the
subsequent falling edge of SCLK.
To perform A/D conversion properly, the BU1S12S1AG-LB needs at least 16 SCLK cycles while CSB is low. If an A/D
conversion is interrupted in the middle of the conversion with CSB going to high before the 16th SCLK falling edge, the
following A/D conversion may not be performed normally. Therefore, it is necessary that equal to or more than 16 falling
edges of SCLK exist while CSB is low.
In addition, SCLK should be held either high or low at the falling edge of CSB. If SCLK is low at the falling edge of CSB,
as shown in Figure 21(b), a Hold mode time length is about a half clock period longer than one if SCLK is high as shown
in Figure 21(a). Therefore, when the BU1S12S1AG-LB is used at the sampling frequency of 1MSPS, it is recommended
to hold SCLK high at the falling edge of CSB, as shown in Figure 21(a), in order to ensure sufficient Track mode time for
the maximum acquisition time.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Track mode
CSB
SCLK
Hold mode
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SDATA
ZERO
ZERO
ZERO
ZERO
4 LEADING ZEROS
High-Z
High-Z
(a) If SCLK is high at the falling edge of CSB
1
2
3
4
5
6
7
8
9
CSB
SCLK
DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
SDATA
10
11
12
13
14
15
16
ZERO
ZERO
ZERO
ZERO
Track mode
Hold mode
4 LEADING ZEROS
High-Z
High-Z
(b) If SCLK is low at the falling edge of CSB
Figure 21. Serial Interface Timing
Figure 5 タイミング図


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