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KM416S4030CT-FL Datasheet(PDF) 11 Page - Samsung semiconductor |
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KM416S4030CT-FL Datasheet(HTML) 11 Page - Samsung semiconductor |
11 / 11 page KM416S4030C REV. 2 June '98 CMOS SDRAM Preliminary SIMPLIFIED TRUTH TABLE (V=Valid, X=Don ′t care, H=Logic high, L=Logic low) Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP A11, A9 ~ A0 Note Register Mode register set H X L L L L X OP code 1,2 Refresh Auto refresh H H L L L H X X 3 Self refresh Entry L 3 Exit L H L H H H X X 3 H X X X 3 Bank active & row addr. H X L L H H X V Row address Read & column address Auto precharge disable H X L H L H X V L Column address (A0 ~ A7) 4 Auto precharge enable H 4,5 Write & column address Auto precharge disable H X L H L L X V L Column address (A0 ~ A7) 4 Auto precharge enable H 4,5 Burst stop H X L H H L X X 6 Precharge Bank selection H X L L H L X V L X All banks X H Clock suspend or active power down Entry H L H X X X X X L V V V Exit L H X X X X X Precharge power down mode Entry H L H X X X X X L H H H Exit L H H X X X X L V V V DQM H V X 7 No operation command H X H X X X X X L H H H 1. OP Code : Operand code A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 CLK cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected. If both BA 0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected. If both BA 0 is "High" and BA 1 is "Low" at read, write, row active and precharge, bank C is selected. If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected. If A 10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at t RP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2) Notes : X |
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