 |
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
|
Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
ADSST-21161NKCA100 Datasheet(PDF) 5 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSST-21161NKCA100 Datasheet(HTML) 5 Page - Analog Devices |
|
|
5 / 28 page  ADSST-SHARC-Melody-Ultra The block diagram of the SHARC Melody Ultra (see ) illustrates the following architectural features: Figure 1 • Computation units (ALU, multiplier, and shifter) with a shared data register file • Data address generators (DAG1, DAG2) • Program sequencer with instruction cache • Timers with event capture modes • On-chip, dual-ported SRAM • External port for interfacing to off-chip memory and pe- ripherals • Host port and SDRAM interface • DMA controller • Enhanced serial ports • JTAG test access port We will use F as our reference. The SHARC Melody Ultra communicates with the host microcontroller using SPI. The SHARC Melody Ultra has an on-chip memory buffer that is used for storing commands/parameters sent by the host to the SHARC Melody Ultra and status information from the SHARC Melody Ultra. There is a defined protocol for passing com- mands and obtaining status information. Once the SHARC Melody Ultra receives a command from the host micro, it will process the command and inform the host micro about the status. These commands initiate actions such as encoding and decoding. Encoding and decoding will result in data processing and the processed data may be delivered over the serial port. For example, while encoding, the MP3 data is accepted through the serial port from peripherals like an ADC or S/PDIF receiver. The MP3 data is then encoded and stored in an on-chip com- pressed data buffer. The SHARC Melody Ultra will prepare the compressed frames in IEC 958 format so that they can be sent out using the serial port or S/PDIF transmitter. Using the serial port, compressed frames can be downloaded to the SHARC Melody Ultra where they can be decoded, and the resulting MP3 data can be sent on the serial port transmitter. While commands and data are transferred between the host microcon- troller and the SHARC Melody Ultra over the SPI, reliable communication needs the help of interrupts and a few general- purpose input/output lines. igure 2 SOFTWARE ARCHITECTURE The audio processors from Analog Devices enable designers to make value additions to product features working off the high- end base functionality. The SHARC Melody Ultra software has the following parts: • Executive kernel • Algorithm as library module The executive kernel has the following functions: • Power-up hardware initialization • Serial port management • Automatic stream detect • Automatic code load • Command processing • Interrupt handling • Data buffer management • Calling library module • Status report The executive kernel is executed as soon as booting takes place. The hardware resources are initialized in the beginning. The command buffer and general-purpose programmable flag pins are initialized. Various data buffers and memory variables are initialized. Interrupts are programmed and enabled. Then, defi- nite signatures are written “Command buffer” to inform the host that the SHARC Melody Ultra is ready to receive the com- mands. Once commands are issued by the host microcontroller, they are executed and appropriate actions take place. Decoding is handled by issuing appropriate commands from the host microcontroller. The kernel communicates with the library module for a particu- lar algorithm in a defined way. The details are found in the specific implementation documents. As the kernel is modular, it is easy to customize to different hardware platforms. Most of the time, users need to change the initialization code to suit the particular codec chosen. DECODING LIBRARY EXECUTIVE KERNEL INPUT STREAM OUTPUT STREAM Figure 3. Software The SHARC Melody Ultra includes a 100 MHz core, dual- ported on-chip SRAM, an integrated I/O processor with multi- processing support, and multiple internal buses to eliminate I/O bottlenecks. The SHARC Melody Ultra offers a Single- Instruction-Multiple-Data (SIMD) architecture, using two computational units. Fabricated in a state of the art, high speed, low power CMOS process, the SHARC Melody Ultra has a 10 ns instruction cycle time. With its SIMD computational hardware running at 100 MHz, the SHARC Melody Ultra can perform 600 million math opera- tions per second. shows performance benchmarks for the SHARC Melody Ultra. Table 1 Rev. 0 | Page 5 of 28 |
Número de pieza similar - ADSST-21161NKCA100 |
|
Descripción similar - ADSST-21161NKCA100 |
|
|
Enlace URL |
| Política de Privacidad |
| ALLDATASHEET.ES |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Spanish ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
