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BD37522FS Datasheet(PDF) 10 Page - Rohm |
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BD37522FS Datasheet(HTML) 10 Page - Rohm |
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10 / 31 page  BD37522FS 10/27 TSZ02201-0C2C0E100470-1-2 © 2015 ROHM Co., Ltd. All rights reserved. www.rohm.com TSZ22111・15・001 16.Dec.2015 Rev.001 Timing Chart CONTROL SIGNAL SPECIFICATION (1) Electrical Specifications and Timing for Bus Lines and I/O Stages Figure 17. Definition of Timing on the I2C-bus Table 1 Characteristics of the SDA and SCL bus lines for I2C-bus devices (Unless otherwise specified, Ta=25°C, VCC=8.5V) Parameter Symbol Fast-mode I2C-bus Unit Min Max 1 SCL clock frequency fSCL 0 400 kHz 2 Bus free time between a STOP and START condition tBUF 1.3 － μs 3 Hold time (repeated) START condition. After this period, the first clock pulse is generated tHD;STA 0.6 － μs 4 LOW period of the SCL clock tLOW 1.3 － μs 5 HIGH period of the SCL clock tHIGH 0.6 － μs 6 Set-up time for a repeated START condition tSU;STA 0.6 － μs 7 Data hold time: tHD;DAT 0.06(Note) － μs 8 Data set-up time tSU;DAT 120 － ns 9 Set-up time for STOP condition tSU;STO 0.6 － μs All values referred to VIH Min and VIL max Levels (see Table 2). (Note) The device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH Min of the SCL signal) in order to bridge the undefined region of the falling edge of SCL. About 7(tHD;DAT), 8(tSU;DAT), make the setup in which the margin is fully in . Table 2 Characteristics of the SDA and SCL I/O stages for I2C-bus devices Parameter Symbol Fast-mode devices Unit Min Max 10 LOW level input voltage: VIL -0.3 +1 V 11 HIGH level input voltage: VIH 2.3 5 V 12 Pulse width of spikes which must be suppressed by the input filter. tSP 0 50 ns 13 LOW level output voltage: at 3mA sink current VOL1 0 0.4 V 14 Input current each I/O pin with an input voltage between 0.4V and 4.5V. II -10 +10 μA SDA S SCL tLOW tR tHD;DAT P tHD;STA tHIGH tBUF tF tSU;DAT tSU;STAT tSU;STOT tSP tHD;STAT Sr P Figure 18. A Command Timing Example in the I2C Data Transmission ｔBUF ：4us ｔHD;STA ：2us ｔHD;DAT ：1us ｔLOW ：3us ｔHIGH ：1us ｔSU;DAT ：1us ｔSU;STO ：2us SCL clock frequency：250kHz SCL SDA tHD;STA :2µs tHD;DAT :1µs tSU;DAT :1µs tSU;STO :2µs tBUF :4µs tLOW :3µs tHIGH :1µs SDA SCL SCL clock frequency : 250kHz |
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