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MC74VHC02 Datasheet(PDF) 1 Page - ON Semiconductor

No. de pieza MC74VHC02
Descripción Electrónicos  Quad 2-Input NOR Gate
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Fabricante Electrónico  ONSEMI [ON Semiconductor]
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MC74VHC02 Datasheet(HTML) 1 Page - ON Semiconductor

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© Semiconductor Components Industries, LLC, 2015
December, 2015 − Rev. 6
1
Publication Order Number:
MC74VHC02/D
MC74VHC02
Quad 2-Input NOR Gate
The MC74VHC02 is an advanced high speed CMOS 2−input NOR
gate fabricated with silicon gate CMOS technology. It achieves high
speed operation similar to equivalent Bipolar Schottky TTL while
maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer
output which provides high noise immunity and stable output. The
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V
systems to 3.0 V systems.
Features
High Speed: tPD = 3.6 ns (Typ) at VCC = 5.0 V
Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
High Noise Immunity: VNIH = VNIL = 28% VCC
Power Down Protection Provided on Inputs
Balanced Propagation Delays
Designed for 2.0 V to 5.5 V Operating Range
Low Noise: VOLP = 0.8 V (Max)
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance:
Human Body Model > 2000 V;
Machine Model > 200 V
Chip Complexity: 40 FETs or 10 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
Figure 1. LOGIC DIAGRAM
1
Y1
2
A1
3
B1
Y4
Y = A + B
4
Y2
5
A2
6
B2
10
Y3
8
A3
9
B3
13
11
A4
12
B4
TSSOP−14
DT SUFFIX
CASE 948G
www.onsemi.com
1
VHC02G
AWLYWW
1
14
SOIC−14
D SUFFIX
CASE 751A
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
1
VHC
02
ALYW
G
G
1
14
A
= Assembly Location
WL, L
= Wafer Lot
Y
= Year
WW, W
= Work Week
G or
G = Pb−Free Package
(Note: Microdot may be in either location)
FUNCTION TABLE
A
L
L
H
H
Inputs
Output
B
L
H
L
H
Y
H
L
L
L
11
12
13
14
8
9
10
5
4
3
2
1
7
6
Y3
A4
B4
Y4
VCC
A3
B3
Y2
B1
A1
Y1
GND
B2
A2
PIN ASSIGNMENT


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