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74AUC1G00GV Datasheet(PDF) 7 Page - NXP Semiconductors |
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74AUC1G00GV Datasheet(HTML) 7 Page - NXP Semiconductors |
7 / 12 page 2002 Nov 12 7 Philips Semiconductors Preliminary specification Single 2-input NAND gate 74AUC1G00 handbook, full pagewidth VEXT VCC VI VO MNA616 D.U.T. CL RT RL RL PULSE GENERATOR Fig.6 Load circuitry for switching times. Definitions for test circuits: RL = Load resistor. CL = Load capacitance including jig and probe capacitance (see Chapter “AC characteristics”). RT = Termination resistance should be equal to the output impedance Zo of the pulse generator. VEXT VCC VI CL RL TPLH/TPHL TPZH/TPHZ TPZL/TPLZ <1.65 V VCC 15 pF 2 k Ω open GND 2 × VCC 1.65 to 1.95 V VCC 30 pF 1 k Ω open GND 2 × VCC 2.3 to 2.7 V VCC 30 pF 0.5 k Ω open GND 2 × VCC |
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