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AD9751AST Datasheet(PDF) 10 Page - Analog Devices

No. de pieza AD9751AST
Descripción Electrónicos  10-Bit, 300 MSPS High-Speed TxDAC D/A Converter
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD9751AST Datasheet(HTML) 10 Page - Analog Devices

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REV. 0
AD9751
–10–
1.2V REF
AVDD
IREF
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
0.1 F
AD9751
REFERENCE
SECTION
ADDITIONAL
EXTERNAL
LOAD
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
Figure 4. Internal Reference Configuration
1.2V REF
AVDD
IREF
CURRENT
SOURCE
ARRAY
REFIO
FSADJ
2k
0.1 F
AD9751
REFERENCE
SECTION
ADDITIONAL
EXTERNAL
LOAD
OPTIONAL
EXTERNAL
REFERENCE
BUFFER
Figure 5. External Reference Configuration
PLL CLOCK MULTIPLIER OPERATION
The Phase Locked Loop (PLL) is intrinsic to the operation of the
AD9751 in that it produces the necessary internally synchronized
2
× clock for the edge-triggered latches, multiplexer, and DAC.
With PLLVDD connected to its supply voltage, the AD9751 is
in PLL ACTIVE mode. Figure 6 shows a functional block dia-
gram of the AD9751 clock control circuitry with PLL active.
The circuitry consists of a phase detector, charge pump, voltage
controlled oscillator (VCO), input data rate range control, clock
logic circuitry, and control input/outputs. The
÷2 logic in the
feedback loop allows the PLL to generate the 2
× clock needed
for the DAC output latch.
Figure 7 defines the input and output timing for the AD9751
with the PLL active. CLK in Figure 7 represents the clock that
is generated external to the AD9751. The input data at both
ports 1 and 2 is latched on the same CLK rising edge. CLK may
be applied as a single-ended signal by tying CLK– to midsupply
and applying CLK to CLK+, or as a differential signal applied
to CLK+ and CLK–.
RESET has no purpose when using the internal PLL and should
be grounded. When the AD9751 is in PLL ACTIVE mode,
PLLLOCK is the output of the internal phase detector. When
locked, the lock output in this mode will be a Logic “1.”
CLKCOM
TO INPUT
LATCHES
CLKVDD
(3.1V TO 3.5V)
PLLLOCK
CHARGE
PUMP
PHASE
DETECTOR
LPF
PLLVDD
VCO
392
1.0 F
3.1V TO
3.5V
RANGE
CONTROL
(
1, 2, 4, 8)
DIV0
DIV1
DIFFERENTIAL
TO
SINGLE-ENDED
AMP
2
TO DAC
LATCH
CLK+
CLK–
AD9751
Figure 6. Clock Circuitry with PLL Active
PORT 1
DATA X
DATA Y
tH
tS
tLPW
tPD
DATA X
DATA Y
1/2 CYCLE +
tPD
PORT 2
IOUTA OR IOUTB
CLK
DATA IN
7a.
PORT 1
DATA X
DATA Z
DATA X
DATA Y
PORT 2
IOUTA OR IOUTB
CLK
DATA IN
DATA Z
DATA W
XXX
DATA W
DATA Y
7b.
Figure 7. DAC Input Timing Requirements with PLL Active
Typically, the VCO can generate outputs of 100 MHz to 400 MHz.
The range control is used to keep the VCO operating within its
designed range, while allowing input clocks as low as 6.25 MHz.
With the PLL active, logic levels at DIV0 and DIV1 determine
the divide (prescaler) ratio of the range controller. Table I gives
the frequency range of the input clock for the different states of
DIV0 and DIV1.
Table I. CLK Rates for DIV0, DIV1 Levels With PLL Active
CLK Frequency
DIV1
DIV0
Range Controller
50 MHz–150 MHz
0
0
÷1
25 MHz–100 MHz
0
1
÷2
12.5 MHz–50 MHz
1
0
÷4
6.25 MHz–25 MHz
1
1
÷8
A 392
Ω resistor and 1.0 µF capacitor connected in series from
LPF to PLLVDD are required to optimize the phase noise vs.
settling/acquisition time characteristics of the PLL. To obtain
optimum noise and distortion performance, PLLVDD should
be set to a voltage level similar to DVDD and CLKVDD.
In general, the best phase noise performance for any PLL range
control setting is achieved with the VCO operating near its
maximum output frequency of 400 MHz.
As stated earlier, applications requiring input data rates below
6.25 MSPS must disable the PLL clock multiplier and provide
an external 2
× reference clock. At higher data rates however,
applications already containing a low phase noise (i.e., jitter)
reference clock that is twice the input data rate should consider
disabling the PLL clock multiplier to achieve the best SNR
performance from the AD9751. Note, the SFDR performance
of the AD9751 remains unaffected with or without the PLL
clock multiplier enabled.


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