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ADS8681IPW Datasheet(PDF) 4 Page - Texas Instruments

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No. de pieza ADS8681IPW
Descripción Electrónicos  16-Bit, High-Speed, Single-Supply, SAR ADC Data Acquisition System with Programmable, Bipolar Input Ranges
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

ADS8681IPW Datasheet(HTML) 4 Page - Texas Instruments

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ALARM/SDO-1/GPO
SDO-0
CONVST/CS
SCLK
AGND
REFIO
REFGND
REFCAP
1
2
3
4
16
15
14
13
ALARM/SDO-1/GPO
SDO-0
CONVST/CS
SDI
RST
DGND
AVDD
SCLK
AGND
REFIO
REFGND
REFCAP
5
6
7
8
12
11
10
9
AIN_P
AIN_GND
DVDD
RVS
4
ADS8681, ADS8685, ADS8689
SBAS633B – FEBRUARY 2016 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: ADS8681 ADS8685 ADS8689
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Copyright © 2016, Texas Instruments Incorporated
5 Pin Configuration and Functions
PW Package
16-Pin TSSOP
Top View (Not to Scale)
RUM Package
16-Pin WQFN
Top View (Not to Scale)
(1)
AI = analog input, AIO = analog input/output, DI = digital input, DO = digital output, and P = power supply.
Pin Functions
NAME
NO.
TYPE(1)
DESCRIPTION
TSSOP
WQFN
AGND
3
1
P
Analog ground pin. Decouple with the AVDD pin.
AIN_GND
8
6
AI
Analog input: negative. Decouple with the AIN_P pin.
AIN_P
7
5
AI
Analog input: positive. Decouple with the AIN_GND pin.
ALARM/SDO-1/GPO
14
12
DO
Multi-function output pin. Active high alarm.
Data output 1 for serial communication. General-purpose output pin.
AVDD
2
16
P
Analog supply pin. Decouple with the AGND pin.
CONVST/CS
11
9
DI
Dual-functionality pin.
Active high logic: conversion start input pin; a CONVST rising edge brings the device from
acquisition phase to conversion phase.
Active low logic: chip-select input pin; the device takes control of the data bus when CS is low;
the SDO-x pins go to tri-state when CS is high.
DGND
1
15
P
Digital ground pin. Decouple with the DVDD pin.
DVDD
16
14
P
Digital supply pin. Decouple with the DGND pin.
REFCAP
6
4
AO
ADC reference buffer decoupling capacitor pin. Decouple with the REFGND pin.
REFGND
5
3
P
Reference ground pin; short to the analog ground plane. Decouple with the REFIO and
REFCAP pins.
REFIO
4
2
AIO
Internal reference output and external reference input pin. Decouple with REFGND.
RST
9
7
DI
Active low logic input to reset the device.
RVS
15
13
DO
Multi-function output pin for serial interface; see the RESET State section.
With CS held high, RVS reflects the status of the internal ADCST signal.
With CS low, the status of RVS depends on the output protocol selection.
SCLK
12
10
DI
Serial communication: clock input pin for the serial interface.
All system-synchronous data transfer protocols are timed with respect to the SCLK signal.
SDI
10
8
DI
Dual function: data input pin for serial communication.
Chain data input during serial communication in daisy-chain mode.
SDO-0
13
11
DO
Serial communication: data output 0


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