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DAC38RF83IAAVR Datasheet(PDF) 10 Page - Texas Instruments

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No. de pieza DAC38RF83IAAVR
Descripción Electrónicos  Dual- or Single-Channel, Single-Ended or Differential-Output, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip PLL
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

DAC38RF83IAAVR Datasheet(HTML) 10 Page - Texas Instruments

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10
DAC38RF80, DAC38RF83, DAC38RF84
DAC38RF85, DAC38RF90, DAC38RF93
SLASEA3 – DECEMBER 2016
www.ti.com
Product Folder Links: DAC38RF80 DAC38RF83 DAC38RF84 DAC38RF85 DAC38RF90 DAC38RF93
Submit Documentation Feedback
Copyright © 2016, Texas Instruments Incorporated
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
Measured with respect to AGND or DGND.
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Supply Voltage Range(2)
VDDDAC1, VDDDIG1, VDDL1_1, VDDL2_1,
VDDCLK1, VDDT1, VDDCLK1, VDDTX1
–0.3
1.3
V
VDDR18, VDDIO18, VDDS18, VDDAPLL18,
VDDAREF18, VDDAOUT18, VDDA18,
VDDAVCO18, VDDTX18
–0.3
2.45
V
VEE18N
2
0.5
V
Voltage between AGND and DGND
–0.3
0.3
V
Pin Voltage Range(2)
RX[0..7]+/-
–0.5
VDDDIG1 + 0.5 V
V
SDEN, SCLK, SDIO, SDO, TXENABLE, ALARM,
RESET, SLEEP, TMS, TCLK, TDI, TDO, TRST,
TESTMODE, GPI0, GPI1, GPO0, GPO1
–0.5
VDDIO + 0.5 V
V
CLKOUT+/-
–0.5
VDDTX18 + 0.5 V
V
DACCLK+/-, SYSREF+/-, DACCLKSE
–0.5
VDDCLK1 + 0.5 V
V
SYNC0+/-, SYNC1+/-
–0.5
VDDS18 + 0.5 V
V
IOUT1+/-, IOUT2+/-
–0.5
VDDAOUT18 + 0.5 V
V
RBIAS, EXTIO, ATEST
–0.5
VDDAOUT18 + 0.5 V
V
IFORCE, VSENSE
–0.5
VDDDIG1 + 0.5 V
V
AMUX1, AMUX0
–0.5
VDDT1 + 0.5 V
V
Peak input current (any input)
20
mA
Peak total input current (all inputs)
–30
mA
Junction temperature TJ
150
°C
Operating free-air temperature, TA
–40
85
°C
Storage temperature, Tstg
–65
150
°C
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2)
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.2 ESD Ratings
VALUE
UNIT
V(ESD)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
±1000
V
Charged-device model (CDM), per JEDEC specification JESD22-
C101(2)
±250
(1)
Prolonged use at this junction temperature may increase the device failure-in-time (FIT) rate
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
TJ
Recommended operating temperature
105
°C
Maximum rated operating junction temperature(1)
125
°C
TA
Recommended free-air temperature
–40
85
°C


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