2

SW

XCON

PWM

Control Logic

+

+

UVP

OVP

3

VIN

Ton

8

VBST

+

6

VFB

OCL

+

+

Soft Start

7

EN

HS

LS

1

GND

SS

Voltage

Reference

Ref

Hiccup

VUVP

VOVP

OCL

threshold

Regulator

UVLO

VREG 5

VREG 5

TSD

5

SS

4

PG

VTHPG

+

One - Shot

Copyright © 2016, Texas Instruments Incorporated

10

TPS562219A, TPS563219A

SLVSDT2 – NOVEMBER 2016

www.ti.com

Product Folder Links: TPS562219A TPS563219A

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Copyright © 2016, Texas Instruments Incorporated

7 Detailed Description

7.1 Overview

The TPS562219A and TPS563219A are 2-A, 3-A synchronous step-down converters. The proprietary D-CAP2™

mode control supports low ESR output capacitors such as specialty polymer capacitors and multi-layer ceramic

capacitors without complex external compensation circuits. The fast transient response of D-CAP2™ mode

control can reduce the output capacitance required to meet a specific level of performance.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 The Adaptive On-Time Control and PWM Operation

The main control loop of the TPS562219A and TPS563219A are adaptive on-time pulse width modulation (PWM)

controller that supports a proprietary D-CAP2™ mode control. The D-CAP2™ mode control combines adaptive

on-time control with an internal compensation circuit for pseudo-fixed frequency and low external component

count configuration with both low ESR and ceramic output capacitors. It is stable even with virtually no ripple at

the output.

At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal one

shot timer expires. This one shot duration is set proportional to the converter input voltage, VIN, and inversely

proportional to the output voltage, VO, to maintain a pseudo-fixed frequency over the input voltage range, hence

it is called adaptive on-time control. The one-shot timer is reset and the high-side MOSFET is turned on again

when the feedback voltage falls below the reference voltage. An internal ramp is added to reference voltage to

simulate output ripple, eliminating the need for ESR induced output ripple from D-CAP2™ mode control.