®

ADS7803

6

STARTING A CONVERSION

A conversion is initiated on the rising edge of the WR input,

with valid signals on A0, A1 and CS. The selected input

channel is sampled for five clock cycles. The successive

approximation conversion takes place during clock cycles 6

through 17.

Figures 2 and 3 show the full conversion sequence and the

timing to initiate a conversion.

A conversion can also be initiated by a rising edge on pin 26,

if a HIGH has been written to D2 of the Special Function

Register, as discussed below.

CALIBRATION

A calibration cycle is initiated automatically upon power-up

(or after a power failure). Calibration can also be initiated by

the user at any time by the rising edge of a minimum 100ns-

wide LOW pulse on the CAL pin (pin 26), or by setting D1

HIGH in the Special Function Register (see SFR section).

A calibration command will initiate a calibration cycle,

regardless of whether a conversion is in process. During a

calibration cycle, convert commands are ignored.

Calibration takes 168 clock cycles, and a normal conversion

(17 clock cycles) is added automatically. Thus, at the end of

a calibration cycle, there is valid conversion data in the

output registers. For maximum accuracy, the supplies and

reference need to be stable during the calibration procedure.

To ensure that supply voltages have settled and are stable, an

internal timer provides a waiting period of 42,425 clock

cycles between power-up/power-failure and the start of the

calibration cycle.

PIN #

NAME

DESCRIPTION

1

SFR

Special Function Register. When connected to a microprocessor address pin, allows access to special functions

through D0 to D7. See the sections discussing the Special Function Register. If not used, connect to DGND. This pin

has an internal pull-down.

2 to 5

AIN0 to AIN3

Analog inputs. Channel 0 to channel 3.

Positive voltage reference input. Normally +5V. Must be

≤V

Negative voltage reference input. Normally 0V.

8

DGND

Digital ground. DGND = 0V.

10 to 17

D0 to D7

Data Bus Input/Output Pins. Normally used to read output data. See section on SFR (Special Function Register) for

other uses.

When SFR is LOW, these function as follows:

10

D7

Data Bit 7 if HBE is LOW; if HBE is HIGH, acts as converter status pin and is HIGH during conversion or calibration,

goes LOW after the conversion is completed. (Acts as an inverted BUSY).

11

D6

Data Bit 6 if HBE is LOW; LOW if HBE is HIGH.

12

D5

Data Bit 5 if HBE is LOW; LOW if HBE is HIGH.

13

D4

Data Bit 4 if HBE is LOW; LOW if HBE is HIGH.

14

D3

Data Bit 3 if HBE is LOW; Data Bit 11 (MSB) if HBE is HIGH.

15

D2

Data Bit 2 if HBE is LOW; Data Bit 10 if HBE is HIGH.

16

D1

Data Bit 1 if HBE is LOW; Data Bit 9 if HBE is HIGH.

17

D0

Data Bit 0 (LSB) if HBE is LOW; Data Bit 8 if HBE is HIGH.

18

RD

Read Input. Active LOW; used to read the data outputs in combination with CS and HBE.

19

CS

Chip Select Input. Active LOW.

20

WR

Write Input. Active LOW; used to start a new conversion and to select an analog channel via address inputs A0 and A1

in combination with CS. The minimum WR pulse LOW width is 100ns.

21

HBE

High Byte Enable. Used to select high or low data output byte in combination with CS and RD, or to select SFR.

22

BUSY

BUSY is LOW during conversion or calibration. BUSY goes HIGH after the conversion is completed.

23

CLK

Clock Input. For internal or external clock operation. For external clock operation, connect pin 23 to a 74HC-compatible

clock source. For internal clock operation, connect pin 23 per the clock operation description.

24 to 25

A0 to A1

Address Inputs. Used to select one of four analog input channels in combination with CS and WR. The address inputs

are latched on the rising edge of WR or CS.

A1

A0

Selected Channel

LOW

LOW

AIN0

LOW

HIGH

AIN1

HIGH

LOW

AIN2

HIGH

HIGH

AIN3

26

CAL

Calibration Input. A calibration cycle is initiated when CAL is LOW. The minimum pulse width of CAL is 100ns. If not

(SHC)

HIGH, pin 26 will be used as an input to control the sample-to-hold timing. A rising edge on pin 26 will switch from

sample-mode to hold-mode and initiate a conversion. This pin has an internal pull-up.

27

AGND

Analog Ground. AGND = 0V.

28

PIN ASSIGNMENTS