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ADS7803BP Datasheet(PDF) 9 Page - Burr-Brown (TI) |
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ADS7803BP Datasheet(HTML) 9 Page - Burr-Brown (TI) |
9 / 13 page 9 ® ADS7803 PIN FUNCTION DESCRIPTION D0 Mode Status If LOW, Transparent Mode enabled for data latches. If HIGH, latched Output Mode enabled. D1 CAL Flag If HIGH, calibration cycle in progress. D2 Pin 26 Status If LOW, pin 26 used as input to initiate calibration cycle. If HIGH, pin 26 used as input to control sample-to-hold timing. D3 Power Down Status If HIGH, in Power Down Mode. D4 Reserved for factory use. D5 POWER FAIL Flag If HIGH, a power supply failure has occurred. (Supply fell below 3V.) D6 CAL ERROR Flag If HIGH, an overflow occurred during calibration. D7 BUSY Flag If HIGH, conversion or calibration in progress. NOTE: These data are transferred to the bus when a read cycle is initiated with SFR and HBE HIGH. Reading the SFR with SFR HIGH and HBE LOW is reserved for factory use at this time, and will yield unpredictable data. TABLE II. Reading the Special Function Register. FIGURE 5. Writing to the SFR. FIGURE 6. Reading the FSR. POWER DOWN MODE Writing a HIGH to D3 in the SFR puts the ADS7803 in the Power Down Mode. Power consumption is reduced to 50 µW and D3 remains HIGH. The internal clock and analog circuitry are turned off, although the output registers and SFR can still be accessed normally. To exit Power Down Mode, either write a LOW to D3 in the SFR, or initiate a calibration by sending a LOW to the CAL pin or writing a HIGH to D1. Note that if the power supply falls below 3V and then recovers, a calibration is automatically initiated, and the SFR will be reset. D3 will be LOW, and the ADS7803 will not be in the Power Down Mode. During Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADS7803 will revert to power down. Also, writing to D1 and D3 in the SFR will initiate a calibration, do a single conversion and revert to the Power Down Mode, in 185 clock cycles. Accurate conver- sion results will be available in the output registers. The activation delay from power down to normal operation is included in the sampling time. No extra time is required, either when coming out of the Power Down Mode or when making a single conversion in the Power Down Mode. OPERATION CS/WR SFR/HBE D0 D1 D2 D3 D5 D4/D6/D7 Enables Transparent Mode for Data Latches LOW HIGH LOW X X X X LOW Enables Latched Output Mode for Data Latches LOW HIGH HIGH(1) X XXX LOW Initiates Calibration Cycle LOW HIGH X HIGH X X X LOW Activates Sample/Hold Control Mode LOW HIGH X X HIGH(1) X X LOW Activates Power Down Mode(2) LOW HIGH X X X HIGH(1) X LOW Resets Power Fail Flag LOW HIGH X X X X LOW LOW NOTES: (1) Writing a LOW here reactivates the standard mode of operation. (2) In Power Down Mode, a pulse on CS and WR will initiate a single conversion, then the ADS7803 will revert to power down. (3) X means it can be either HIGH or LOW without affecting this action. Writing HIGH to D4 or D6, or writing with SFR HIGH and HBE LOW, may result in unpredictable behavior. These modes are reserved for factory use at this time. TABLE III. Writing to the Special Function Register. SAMPLE/HOLD CONTROL MODE With D2 in the SFR HIGH, a rising edge input on pin 26 will switch the ADS7803 from sample-mode to hold-mode with a 5ns aperture delay. This also initiates a conversion, which will start within 1.5 CLK cycles. This mode allows full control over the sample-to-hold tim- ing, which is especially useful where external events trigger sampling timing. In the Sample/Hold Control Mode, pin 26 must be held LOW a minimum of 2.5 µs between conversions to allow accurate acquisition of input signals. Also, offset error will increase in this mode, since auto-zeroing of the comparator is not synchronized to the sampling. Minimum offset is achieved by synchronizing the sampling signal to CLK, whether internal or external. Ideally, the sampling signal D0 - D7 Valid Data SFR HBE WR CS t 5 t 16 t 17 V IL V IH t 2 t 3 t 1 t 6 D0 - D7 SFR Data SFR HBE RD CS t 11 t 14 V IH t 10 t 8 t 11 t 13 t 12 t 12 |
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