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TPS3852H33DRBT Datasheet(PDF) 6 Page - Texas Instruments |
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TPS3852H33DRBT Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 30 page  VDD RESET WDI WDO tRST tRST tRST VPOR VITN t < tWDU tWDL < t < tWDU (1) t < tWDL X VITN + VHYST VITN X tRST-DEL t < tWDU 6 TPS3852 SBVS302 – NOVEMBER 2016 www.ti.com Product Folder Links: TPS3852 Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated (1) SET1 = 0 means VSET1 < VIL, SET1 = 1 means VSET1 > VIH 6.6 Timing Requirements At VITN + VHYST ≤ VDD ≤ 6.5 V over the operating temperature range of –40°C ≤ TA, T J ≤ 125°C, unless otherwise noted. The open-drain pull-up resistors are 10 kΩ for each output. Typical values are at TJ = 25°C. MIN TYP MAX UNIT tINIT CWD pin evaluation period 381 µs Minimum MR, SET1 pin pulse duration 1 µs Startup delay 300 µs RESET FUNCTION tRST Reset timeout period 170 200 230 ms tRST-DEL VDD to RESET delay VDD = VITN + VHYST + 2.5% 35 µs VDD = VITN - 2.5% 17 tMR-DEL MR to RESET delay 200 ns Watchdog Function tWDL Window watchdog lower boundary CWD = NC, SET1 = 0(1) Watchdog disabled CWD = NC, SET1 = 1(1) 680 800 920 ms CWD = 10kΩ to VDD, SET1 = 0(1) Watchdog disabled CWD = 10kΩ to VDD, SET1 = 1(1) 1.5 1.85 2.2 ms tWDU Window watchdog upper boundary CWD = NC, SET1 = 0(1) Watchdog disabled CWD = NC, SET1 = 1(1) 1360 1600 1840 ms CWD = 10kΩ to VDD, SET1 = 0(1) Watchdog disabled CWD = 10kΩ to VDD, SET1 = 1(1) 9.3 11.0 12.7 ms tWD- setup Setup time required for part to respond to changes on WDI after being enabled 150 µs Minimum WDI pulse width 50 ns tWD-DEL WDI to WDO Delay 50 ns (1) See Figure 2 for WDI timing requirements. Figure 1. Timing Diagram |
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