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UC1825A-SP Datasheet(PDF) 8 Page - Texas Instruments

No. de pieza UC1825A-SP
Descripción Electrónicos  Class-V, Radiation Hardened High-Speed PWM Controller
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Fabricante Electrónico  TI1 [Texas Instruments]
Página de inicio  http://www.ti.com
Logo TI1 - Texas Instruments

UC1825A-SP Datasheet(HTML) 8 Page - Texas Instruments

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UDG-02091
OSC
PWM Latch
Fault Latch
(60%)
E / A
1.2 V
1 V
0.2 V
5 V
1.25 V
UVLO
T
Restart
Delay
Latch
Restart
Delay
4
5
6
7
3
2
1
8
9
15
10
16
12
14
11
13
CLK / LEB
RAMP
EAOUT
NI
INV
SS
Soft Start Complete
ILIM
GND
PGND
OUTB
OUTA
R
R
R
S
D
S
D
S
Current
Limit
Overcurrent
9.2 V / 8.4 V
PWM Comparator
Internal
Bias
4 V
5.1 VREF
VREF
5.1 V
On / Off
CT
RT
VCC
VC
VREF Good
9 A
250 A
8
UC1825A-SP
SLUS873C – JANUARY 2009 – REVISED DECEMBER 2016
www.ti.com
Product Folder Links: UC1825A-SP
Submit Documentation Feedback
Copyright © 2009–2016, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
UC1825A-SP PWM controller is an improved version of the standard UC1825 family. Performance
enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth product is
12 MHz, while input offset is 2 mV. Current limit threshold is assured to a tolerance of 5%. Oscillator discharge
current is specified to 10 mA for accurate dead time control. Frequency accuracy is improved to 6%. Start-up
supply current, typically 100 µA, is ideal for offline applications. The output drivers are redesigned to actively sink
current during UVLO at no expense to the start-up current specifications. In addition, each output is capable of
2-A peak currents during transitions.
8.2 Functional Block Diagram
8.3 Feature Description
UC1825A-SP can be configured as current mode controller, used to support various topologies such as forward,
flyback, Buck, Boost and using an external interface circuit will also support half-bridge, full bridge, and push-pull
configurations.
8.3.1 Leading Edge Blanking
The UC1825A-SP performs fixed frequency pulse width modulation control. The UC1825A-SP outputs are
alternately controlled. During every other cycle, one output is off. Each output then switches at one-half the
oscillator frequency, varying in duty cycle from 0 to less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the
oscillator. On the falling edge of the clock, the appropriate output is driven high. The end of the pulse is
controlled by the PWM comparator, current limit comparator, or the overcurrent comparator.
Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates
the pulse. Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time
after the start of the pulse. This allows noise inherent with switched mode power conversion to be rejected. The
PWM ramp input may not require any filtering as result of leading edge blanking.


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