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TPS54262MPWPTEP Datasheet(PDF) 11 Page - Texas Instruments |
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TPS54262MPWPTEP Datasheet(HTML) 11 Page - Texas Instruments |
11 / 48 page 11 TPS54262-EP www.ti.com SLVSDP3 – DECEMBER 2016 Product Folder Links: TPS54262-EP Submit Documentation Feedback Copyright © 2016, Texas Instruments Incorporated Feature Description (continued) Table 1. Load Conditions LOAD CONDITION OUTPUT TRACKING Nominal load in CCM VReg tracks VIN approximately as: VReg = 95% (VIN – ILoad × 0.5) No load/light load in LPM To enable the tracking feature, following conditions should be met: 1) fSW < 600 kHz 2) VReg < 8 V, typical (related to VIN falling threshold when LPM is disabled) 7.3.4 Enable and Shutdown The EN pin (pin 5) provides electrical ON/OFF control of the regulator. Once the EN pin voltage exceeds the upper threshold voltage (VIH), the regulator starts operating and the internal soft start begins to ramp. If the EN pin voltage is pulled below the lower threshold voltage (VIL), the regulator stops switching and the internal soft start resets. Connecting this pin to ground or to any voltage less than VIL disables the regulator and causes the device to shut down. This pin must have an external pullup or pulldown to change the state of the device. 7.3.5 Soft Start An external soft-start capacitor is connected to SS pin (pin 11) to set the minimum time to reach the desired regulated output voltage (VReg) during power-up cycle. This prevents the output voltage from overshooting when the device is powered up. This is also useful when the load requires a controlled voltage slew rate, and also helps to limit the current drawn from the input voltage supply line. For proper operation, the following conditions must be satisfied during power up and after a short circuit event: • VIN – VReg > 2.5 V • Load current < 1 A, until RST goes high The power-up current limit (30% of the typical current limit value) is released after the feedback voltage (at VSENSE pin) is high enough such that RST is asserted high. The recommended value of soft-start capacitor is 100 nF (typical) for start-up load current of 1 A (maximum). 7.3.6 Oscillator Frequency The oscillator frequency can be set by connecting an external resistor (R8 in Functional Block Diagram) to RT pin (pin 6). Figure 10 shows the relation between the resistor value (RT) and switching frequency (fsw). The switching frequency can be set in the range 200 kHz to 2200 kHz. In addition, the switching frequency can be imposed externally by a clock signal (fext) at the SYNC pin. 7.3.6.1 Selecting the Switching Frequency A power supply switching at a higher switching frequency allows use of lower value inductor and smaller output capacitor compared to a power supply that switches at a lower frequency. Typically, the user will want to choose the highest switching frequency possible because this will produce the smallest solution size. The switching frequency that can be selected is limited by the following factors: • The input voltage • The minimum target regulated voltage • Minimum on-time of the internal switching transistor • Frequency shift limitation Selecting lower switching frequency results in using an inductor and capacitor of a larger value, where as selecting higher switching frequency results in higher switching and gate drive power losses. Therefore, a tradeoff must be made between physical size of the power supply and the power dissipation at the system/ application level. |
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