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TPS3813K33-EP Datasheet(PDF) 6 Page - Texas Instruments |
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TPS3813K33-EP Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 24 page  6 TPS3813J25, TPS3813L30, TPS3813K33, TPS3813I50 SLVS331H – DECEMBER 2000 – REVISED JULY 2016 www.ti.com Product Folder Links: TPS3813J25 TPS3813L30 TPS3813K33 TPS3813I50 Submit Documentation Feedback Copyright © 2000–2016, Texas Instruments Incorporated (1) The lowest supply voltage at which RESET becomes active. tr, VDD ≥ 15 µs/V. (2) To ensure best stability of the threshold voltage, a bypass capacitor (ceramic, 0.1 µF) must be placed near to the supply terminals. 7.5 Electrical Characteristics Over recommended operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOL Low-level output voltage VDD = 2 V to 6 V, IOL = 500 µA 0.2 V VDD = 3.3 V IOL = 2 mA 0.4 VDD = 6 V, IOL = 4 mA 0.4 VPOR Power up reset voltage (1) VDD ≥ 1.1 V, IOL = 50 µA 0.2 V VIT Negative-going input threshold voltage (2) TPS3813J25 TA = –40°C to +85°C 2.2 2.25 2.3 V TPS3813L30 2.58 2.64 2.7 TPS3813K33 2.87 2.93 3 TPS3813I50 4.45 4.55 4.65 Vhys Hysteresis TPS3813J25 30 mV TPS3813L30 35 TPS3813K33 40 TPS3813I50 60 IIH High-level input current WDI, WDR WDI = VDD = 6 V, WDR = VDD = 6 V –25 25 nA WDT WDT = VDD = 6 V, VDD > VIT, RESET = High –100 100 IIL Low-level input current WDI, WDR WDI = 0 V, WDR = 0 V, VDD = 6 V –25 25 WDT WDT = 0 V, VDD > VIT, RESET = High –100 100 IOH High-level output current VDD = VIT + 0.2 V, VOH = VDD 25 nA IDD Supply current VDD = 2-V output unconnected 9 13 µA VDD = 5-V output unconnected 20 25 Ci Input capacitance VI = 0 V to VDD 5 pF 7.6 Timing Requirements At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to +85°C. MIN TYP MAX UNIT tw Pulse width at VDD VDD = VIT– + 0.2 V, VDD = VIT– – 0.2 V 3 µs (1) 155 pF < C(ext) < 63 nF (2) (C(ext) ÷ 15.55 pF + 1) × 6.25 ms 7.7 Switching Characteristics At RL = 1 MΩ, CL = 50 pF, and TA = –40°C to +85°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT td Delay time VDD ≥ VIT + 0.2 V, See Figure 1 20 25 30 ms tt(out) Watchdog time-out Upper limit WDT = 0 V 0.2 0.25 0.3 s WDT = VDD 2 2.5 3 WDT = programmable (1) See (2) ms Watchdog window ratio WDR = 0 V, WDT = 0 V 1:31.8 WDR = 0 V, WDT = VDD 1:32 WDR = 0 V, WDT = programmable 1:25.8 WDR = VDD, WDT = 0 V 1:124.9 WDR = VDD, WDT = VDD 1:127.7 WDR = VDD, WDT = programmable 1:64.5 tPHL Propagation (delay) time, high-to-low-level output VDD to RESET delay VIL = VIT – 0.2 V, VIH = VIT + 0.2 V 30 50 µs |
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