MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

3–1

REV 0.2

3/98

Product Preview

Dual Differential LVPECL to

TTL Translator

The MC100LVELT23 is a dual differential LVPECL to TTL translator.

Because LVPECL (Positive ECL) levels are used only +3.3V and ground

are required. The small outline 8-lead SOIC package and the dual gate

design of the LVELT23 makes it ideal for applications which require the

translation of a clock and a data signal.

The LVELT23 is available in only the ECL 100K standard. Since there

are no LVPECL outputs or an external VBB reference, the LVELT23 does

not require both ECL standard versions. The LVPECL inputs are

differential; there is no specified difference between the differential input

10H and 100K standards. Therefore, the MC100LVELT23 can accept any

standard differential LVPECL input referenced from a VCC of 3.3V.

Note:

1)

Pulling the output higher than VCC is not recommended. Doing so

causes excessive leakage and possible latchup leading to reliability

risk.

1

2

3

45

6

7

8

Q0

GND

VCC

Figure 1. 8–Lead Pinout and Logic Diagram

D0

Q1

D1

D1

D0

LVPECL

TTL

This document contains information on a product under development. Motorola reserves the right to

change or discontinue this product without notice.

MC100LVELT23

PIN

FUNCTION

Qn

TTL Outputs

Dn

Diff LVPECL Inputs

VCC

+3.3V Supply

GND

Ground

PIN DESCRIPTION

D SUFFIX

8–LEAD PLASTIC SOIC PACKAGE

CASE 751–05