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T89C5115 Datasheet(PDF) 89 Page - ATMEL Corporation |
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T89C5115 Datasheet(HTML) 89 Page - ATMEL Corporation |
89 / 105 page 89 T89C5115 4128A–8051–04/02 Table 65. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register 1 Reset Value = xxxx xx0xb bit addressable 76 54 32 1 0 - - - - - - PADCL - Bit Number Bit Mnemonic Description 7- Reserved The value read from this bit is indeterminate. Do not set this bit. 6- Reserved The value read from this bit is indeterminate. Do not set this bit. 5- Reserved The value read from this bit is indeterminate. Do not set this bit. 4- Reserved The value read from this bit is indeterminate. Do not set this bit. 3- Reserved The value read from this bit is indeterminate. Do not set this bit. 2- Reserved The value read from this bit is indeterminate. Do not set this bit. 1 PADCL ADC Interrupt Priority level less significant bit. Refer to PSPIH for priority level. 0- Reserved The value read from this bit is indeterminate. Do not set this bit. |
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