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AD9694-500EBZ Datasheet(PDF) 8 Page - Analog Devices |
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AD9694-500EBZ Datasheet(HTML) 8 Page - Analog Devices |
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8 / 101 page  AD9694 Data Sheet Rev. 0 | Page 8 of 101 Parameter Min Typ Max Unit LOGIC INPUTS (PDWN/STBY) Logic Compliance CMOS Logic 1 Voltage 0.65 × SPIVDD V Logic 0 Voltage 0 0.35 × SPIVDD V Input Resistance 10 MΩ LOGIC INPUTS (SDIO, SCLK, CSB) Logic Compliance CMOS Logic 1 Voltage 0.65 × SPIVDD V Logic 0 Voltage 0 0.35 × SPIVDD V Input Resistance 56 kΩ LOGIC OUTPUT (SDIO) Logic Compliance CMOS Logic 1 Voltage (IOH = 800 µA) SPIVDD − 0.45 V V Logic 0 Voltage (IOL = 50 µA) 0 0.45 V SYNCIN INPUT (SYNCINB+AB/SYNCINB−AB/ SYNCINB+CD/SYNCINB−CD) Logic Compliance LVDS/LVPECL/CMOS Differential Input Voltage 400 800 1800 mV p-p Input Common-Mode Voltage 0.6 0.69 2.2 V Input Resistance (Differential) 18 22 kΩ Input Capacitance (Single Ended per Pin) 0.7 pF LOGIC OUTPUTS (FD_A, FD_B) Logic Compliance CMOS Logic 1 Voltage 0.8 × SPIVDD V Logic 0 Voltage 0 0.5 V Input Resistance 56 kΩ DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3) Logic Compliance CML Differential Output Voltage 455.8 mV p-p Short-Circuit Current (ID SHORT) 15 mA Differential Termination Impedance 100 Ω 1 DC-coupled input only. SWITCHING SPECIFICATIONS AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.8 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.8 V, SPIVDD = 1.8 V, 500 MSPS, clock divider = 4, 1.8 V p-p full-scale differential input, 0.5 V internal reference, AIN = −1.0 dBFS, default SPI settings, unless otherwise noted. Minimum and maximum specifications are guaranteed for the full operating junction temperature (TJ) range of −40°C to +105°C. Typical specifications represent performance at TJ = 50°C (TA = 25°C). Table 6. Parameter Min Typ Max Unit CLOCK Clock Rate (at CLK+/CLK− Pins) 0.3 2.4 GHz Maximum Sample Rate1 600 MSPS Minimum Sample Rate2 240 MSPS Clock Pulse Width High 125 ps Clock Pulse Width Low 125 ps OUTPUT PARAMETERS Unit Interval (UI)3 62.5 100 ps Rise Time (tR) (20% to 80% into 100 Ω Load) 31.25 ps Fall Time (tF) (20% to 80% into 100 Ω Load) 31.37 ps PLL Lock Time 5 ms Data Rate per Channel (Nonreturn-to-Zero (NRZ))4 1.5625 10 15 Gbps |
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