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ADA4805-1AKSZ-EBZ Datasheet(PDF) 7 Page - Analog Devices

No. de pieza ADA4805-1AKSZ-EBZ
Descripción Electrónicos  0.2 關V/째C Offset Drift, 105 MHz Low Power, Low Noise, Rail-to-Rail Amplifiers
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

ADA4805-1AKSZ-EBZ Datasheet(HTML) 7 Page - Analog Devices

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Data Sheet
ADA4805-1/ADA4805-2
Rev. B | Page 7 of 25
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Rating
Supply Voltage
11 V
Power Dissipation
See Figure 3
Common-Mode Input Voltage
−VS − 0.7 V to +VS + 0.7 V
Differential Input Voltage
±1 V
Storage Temperature Range
−65°C to +125°C
Operating Temperature Range
−40°C to +125°C
Lead Temperature (Soldering, 10 sec)
300°C
Junction Temperature
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
θJA is specified for the worst case conditions, that is, θJA is specified
for a device soldered in a circuit board for surface-mount packages.
Table 6 lists the θJA for the ADA4805-1/ADA4805-2.
Table 6. Thermal Resistance
Package Type
θJA
Unit
6-Lead SC70
223.6
°C/W
6-Lead SOT-23
209.1
°C/W
8-Lead MSOP
123.8
°C/W
10-Lead LFCSP
51.4
°C/W
MAXIMUM POWER DISSIPATION
The maximum safe power dissipation for the ADA4805-1/
ADA4805-2 is limited by the associated rise in junction
temperature (TJ) on the die. At approximately 150C, which is
the glass transition temperature, the properties of the plastic
change. Even temporarily exceeding this temperature limit may
change the stresses that the package exerts on the die, permanently
shifting the parametric performance of the ADA4805-1/ADA4805-2.
Exceeding a junction temperature of 175C for an extended
period of time can result in changes in silicon devices, potentially
causing degradation or loss of functionality.
The power dissipated in the package (PD) is the sum of the
quiescent power dissipation and the power dissipated in the die
due to the ADA4805-1/ADA4805-2 output load drive.
The quiescent power dissipation is the voltage between the supply
pins (VS) multiplied by the quiescent current (IS).
PD = Quiescent Power + (Total Drive Power − Load Power)

L
OUT
L
OUT
S
S
S
D
R
V
R
V
V
I
V
P
2
2


RMS output voltages must be considered. If RL is referenced
to −VS, as in single-supply operation, the total drive power is
VS × IOUT. If the rms signal levels are indeterminate, consider the
worst case, when VOUT = VS/4 for RL to midsupply.
 
L
S
S
S
D
R
V
I
V
P
2
4
/
In single-supply operation with RL referenced to −VS, worst case
is VOUT = VS/2.
Airflow increases heat dissipation, effectively reducing θJA. Also,
more metal directly in contact with the package leads and
exposed pad from metal traces, through holes, ground, and
power planes reduces θJA.
Figure 3 shows the maximum safe power dissipation in the
package vs. the ambient temperature on a JEDEC standard,
4-layer board. θJA values are approximations.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–50
–30
–10
10
30
50
70
90
110
130
AMBIENT TEMPERATURE (°C)
TJ = 150°C
6-LEAD SC70
6-LEAD SOT-23
8-LEAD MSOP
10-LEAD LFCSP
Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION


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