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S-19104N12H-M5T1U Datasheet(PDF) 16 Page - Seiko Instruments Inc |
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S-19104N12H-M5T1U Datasheet(HTML) 16 Page - Seiko Instruments Inc |
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16 / 40 page  FOR AUTOMOTIVE 105°C OPERATION BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN S-19104/19106 Series Rev.1.2_00 16 Operation 1. Basic operation 1. 1 S-19104/19106 Series N type (1) When the power supply voltage (VDD) is the minimum operation voltage or higher, and the SENSE pin voltage (VSENSE) is the release voltage ( +VDET) or higher, the Nch transistor is turned off to output VDD ("H") when the output is pulled up. Since the Nch transistor (N1) is turned off, the input voltage to the comparator is (RB + RC ) • VSENSE RA + RB + RC . (2) Even if VSENSE decreases to +VDET or lower, VDD is output when VSENSE is higher than the detection voltage ( −VDET). When VSENSE decreases to −VDET or lower (point A in Figure 21), the Nch transistor is turned on. And then VSS ("L") is output from the OUT pin after the elapse of the detection delay time (tDET). At this time, N1 is turned on, and the input voltage to the comparator is RB • VSENSE RA + RB . (3) Even if VSENSE further decreases to the IC's minimum operation voltage or lower, the output from the OUT pin is stable when VDD is minimum operation voltage or higher. (4) Even if VSENSE exceeds −VDET, VSS is output when VSENSE is lower than +VDET. (5) When VSENSE increases to +VDET or higher (point B in Figure 21), the Nch transistor is turned off. And then VDD is output from the OUT pin after the elapse of the release delay time (tRESET) when the output is pulled up. VSS *1 *1 VREF − + OUT VDD *1 SENSE N1 RB RC RA VDD V + R 100 k Ω VSENSE Nch Delay circuit *1 CD CD *1. Parasitic diode Figure 20 Operation of S-19104/19106 Series N Type A B VSENSE VSS VDD VSS (1) (2) (3) (5) (4) tDET tRESET Hysteresis width (VHYS) Minimum operation voltage Output from OUT pin Release voltage ( +VDET) Detection voltage ( −VDET) Figure 21 Timing Chart of S-19104/19106 Series N Type |
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