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SI512-13 Datasheet(PDF) 5 Page - Silicon Laboratories |
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SI512-13 Datasheet(HTML) 5 Page - Silicon Laboratories |
5 / 20 page Si512/513 Rev. 1.0 5 Table 2. Output Clock Frequency Characteristics VDD = 1.8 V ±5%, 2.5 or 3.3 V ±10%, TA = –40 to +85 oC Parameter Symbol Test Condition Min Typ Max Units Nominal Frequency FO CMOS, Dual CMOS 0.1 — 212.5 MHz FO LVDS/LVPECL/HCSL 0.1 — 250 MHz Total Stability* Frequency Stability Grade C –30 +30 ppm Frequency Stability Grade B –50 +50 ppm Frequency Stability Grade A –100 +100 ppm Temperature Stability Frequency Stability Grade C –20 +20 ppm Frequency Stability Grade B –25 +25 ppm Frequency Stability Grade A –50 +50 ppm Startup Time TSU Minimum VDD to output frequency (FO) within specification —— 10 ms Disable Time TD FO 10 MHz — — 5 µs FO < 10 MHz — — 40 µs Enable Time TE FO 10 MHz — — 20 µs FO < 10 MHz — — 60 µs Settling Time after FS Change tFRQ —— 10 ms *Note: Total stability includes initial accuracy, operating temperature, supply voltage change, load change, shock and vibration (not under operation), and 10 years aging at 40 °C. |
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