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Si5344H Datasheet(PDF) 8 Page - Silicon Laboratories |
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Si5344H Datasheet(HTML) 8 Page - Silicon Laboratories |
8 / 56 page Si5344H/42H 8 Rev. 1.0 Table 5. Differential Clock Output Specifications (VDD = 1.8 V ±5%, VDDA = 3.3V ±5%, VDDO = 1.8 V ±5%, 2.5 V ±5%, or 3.3 V ±5%, TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Output Frequency: High-Speed Output fOUT MultiSynth not used Only AC-coupled 3.3V differen- tial high-speed output is sup- ported for fOUT >1.5 GHz 0.615 — 1.195833 GHz 1.23 — 2.39166 2.46 — 2.75 Output Frequency: MultiSynth Output2 fOUT MultiSynth used for any-fre- quency support (all output formats) 0.0001 — 717.5 MHz Duty Cycle DC fOUT < 400 MHz 48 — 52 % 400 MHz < fOUT < 1.37 GHz 45 — 55 1.37 GHz <fOUT <2.75 GHz 25 — 75 Output-Output Skew Using Same Multi- Synth TSKS Outputs on same MultiSynth (Measured at 717.5 MHz) —— 65 ps Output-Output Skew between MultiSynths TSKD Outputs from different Multi- Synths (Measured at 717.5 MHz) —— 90 ps OUT-OUT Skew TSK_OUT Measured from the positive to negative output pins —0 50 ps Note: 1. For normal mode, the amplitude and common-mode settings are programmable through register settings and can be stored in NVM. Each output driver can be programmed independently. The typical LVDS maximum is 100 mV (or 80 mV) higher than the TIA/EIA-644 maximum. When in LVPECL mode and fOUT>717.5 MHz note VOUT may not meet standard LVPECL levels, but provides the greatest output voltage swing. Also note that the output voltage swing specifications are given in peak-to- peak single-ended swing. 2. Max frequency using MultiSynth outputs is determined by the VCO frequency. Please use ClockBuilder Pro to determine the maximum output frequency for any given frequency plan. 3. High-speed outputs indicates no multiSynth is used (i.e., not fractional synthesis). 4. Not all combinations of voltage swing and common mode voltages settings are possible. See the reference manual for details. 5. Measured for 156.25 MHz carrier frequency. 100 mVpp sinewave noise added to VDDO = 3.3 V and noise spur amplitude measured. 6. Measured across two adjacent outputs, both in LVDS mode, with the victim running at 155.52 MHz and the aggressor at 156.25 MHz. Refer to “AN862: Optimizing Si534x Jitter Performance in Next Generation Internet Infrastructure Systems” for guidance on crosstalk optimization. Note that all active outputs must be terminated when measuring crosstalk. OUTx OUTx Vpp_se Vpp_se Vpp_diff = 2*Vpp_se Vcm Vcm |
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