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SL28PCIE50 Datasheet(PDF) 7 Page - Silicon Laboratories |
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SL28PCIE50 Datasheet(HTML) 7 Page - Silicon Laboratories |
7 / 17 page SL28PCIe50 DOC#: SP-AP-0758 (Rev. AA) Page 7 of 16 Byte 5: Control Register 5 Bit @Pup Type Name Description 7 0 R/W REF0_BIT2 Slew Rate Contorl for REF clocks 6 1 R/W REF0_BIT1 5 0 R/W REF0_BIT0 4 0 R/W REF1_BIT2 3 1 R/W REF1_BIT1 2 0 R/W REF1_BIT0 1 0 R/W TEST_MODE_ENTRY Allows entry into test mode 0 = Normal Operation, 1 = Enter test mode(s) 0 0 R/W TEST _MODE_SEL Test mode select either REF/N or tri-state 0 = All outputs tri-state, 1 = All output REF/N Byte 6: Control Register 6 Bit @Pup Type Name Description 7 0 R/W REF2_BIT2 Slew Rate Control for REF clocks 6 1 R/W REF2_BIT1 5 0 R/W REF2_BIT0 4 0 R/W Wireless Friendly Mode One-bit slew rate control. Set all SE clocks to 101 setting 0=Disabled; 1=Enabled 3 1 R/W PLL1_SS_EN Spread Enabled for PLL1 0=Spread Disabled; 1=Spread Enabled 2 0 R/W PLL1_SS_DC Spread Profile 0=-0.5%; 1=+/-0.25% 1 0 R/W CONF_SE2_FS CONF_SE2 Frequecy Select 0=24.576MHz, 1=12MHz (Note: Byte 6<1> only applies when Byte 6<0>=0 0 0 R/W CONF_SE2_PLL_SEL PLL source for CONF_SE2 output 0=PLL3; (Note: Byte6<0> = 0, Table 7 applies for CONF_SE2) 1=PLL2; (Note: Byte6<0> = 1, Table 6 applies for CONF_SE2) M ode BIT2 BIT1 BIT0 Buffe r Str e ngth 000 Str ong 001 Def ault 010 011 100 Wireless Friendly 101 110 111 We ak M ode BIT2 BIT1 BIT0 Buffe r Str e ngth 000 Str ong 001 Def ault 010 011 100 Wireless Friendly 101 110 111 We ak |
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