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AD8390AACPZ-R2 Datasheet(PDF) 11 Page - Analog Devices |
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AD8390AACPZ-R2 Datasheet(HTML) 11 Page - Analog Devices |
11 / 13 page AD8390A Data Sheet Rev. C | Page 10 of 12 APPLICATIONS INFORMATION SUPPLIES, GROUNDING, AND LAYOUT The AD8390A can be powered from either single or dual supplies, with the total supply voltage ranging from 10 V to 24 V. For optimum performance, use well-regulated low ripple supplies. As with all high speed amplifiers, pay close attention to supply decoupling, grounding, and overall board layout. Provide low frequency supply decoupling with 10 µF tantalum capacitors from each supply to ground. In addition, decouple all supply pins with 0.1 µF quality ceramic chip capacitors placed as close as possible to the driver. Use an internal low impedance ground plane to provide a common ground point for all driver and decoupling capacitor ground requirements. Whenever possible, use separate ground planes for analog and digital circuitry. Follow high speed layout techniques to minimize parasitic capacitance around the inverting inputs. Some practical examples of these techniques are keeping feedback traces as short as possible and clearing away ground plane in the area of the inverting inputs. Keep input and output traces as short as possible and as far apart from each other as practical to minimize crosstalk. Keep all differential signal traces as symmetrical as possible. VCOM PIN By design, the VCOM pin is internally biased at midsupply, eliminating the need for external resistors. However, the designer may set VCOM to other voltage levels with an external low impedance source. When the VCOM pin is left unconnected, decouple it with a 0.1 µF capacitor to ground, placed in close proximity to the AD8390A. With dual equal supplies, connect the VCOM pin directly to ground to bias the outputs at midsupply, eliminating the need for the external decoupling capacitor. POWER MANAGEMENT The AD8390A offers significant versatility for maximizing efficiency while maintaining optimal levels of performance. Optimizing driver efficiency while delivering the required signal level is accomplished with two on-chip power management features: two PD pins to select one of four bias modes and an IADJ pin for fine bias adjustments. PD(1:0) Pins Two CMOS-compatible logic pins, PD1 and PD0, select one of three active power levels and a power-down mode. The digital ground pin (DGND) is the logic ground reference for the PD(1:0) pins. PD(1:0) = (0,0) is the power-down mode. The PD pins are internally connected to DGND via termination resistors. When the PD pins are left unconnected, the AD8390A is in power-down mode. The AD8390A exhibits a low output impedance in the three active modes. The output impedance in the power-down mode is high but undefined and may not be suitable for systems that rely on a high impedance OFF state, such as multiplexing. IADJ Pin The IADJ pin provides bias current fine-tuning. With the IADJ pin unconnected, the bias currents are internally set to 10 mA, 6.7 mA, and 3.8 mA for the three active modes. With the IADJ pin connected to the negative supply (VEE), the bias currents are reduced by approximately 50%. A resistor, RADJ, connected between the IADJ pin and the negative supply, provides fine bias adjustment as shown in Figure 8. Table 5. PD and IADJ Selection Guide PD1 PD0 RADJ (Ω) IQ (mA) 1 1 ∞ 10.0 1 0 ∞ 6.7 0 1 ∞ 3.8 0 0 ∞ 0.67 1 1 0 5.5 1 0 0 4.0 0 1 0 2.6 0 0 0 0.56 |
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