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AD5675ARUZ-REEL7 Datasheet(PDF) 10 Page - Analog Devices

No. de pieza AD5675ARUZ-REEL7
Descripción Electrónicos  Base station power amplifiers
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Fabricante Electrónico  AD [Analog Devices]
Página de inicio  http://www.analog.com
Logo AD - Analog Devices

AD5675ARUZ-REEL7 Datasheet(HTML) 10 Page - Analog Devices

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Data Sheet
AD5675
Rev. B | Page 9 of 26
14
13
12
1
3
4
RESET
15 VREF
SDA
LDAC
11 GND
VDD
SCL
2
VLOGIC
A0
5
A1
AD5675
TOP VIEW
(Not to Scale)
NOTES
1. NIC = NO INTERNAL CONNECTION.
2. EXPOSED PAD. THE EXPOSED PAD
MUST BE TIED TO GND.
Figure 5. LFCSP Pin Configuration
Table 8. LFCSP Function Descriptions
Pin No.
Mnemonic
Description
1
VDD
Power Supply Input. The AD5675 operates from 2.7 V to 5.5 V. Decouple the VDD supply with a 10 µF capacitor in
parallel with a 0.1 µF capacitor to GND.
2
VLOGIC
Digital Power Supply. The voltage on this pin ranges from 1.8 V to 5.5 V.
3
SCL
Serial Clock Line. This pin is used in conjunction with the SDA line to clock data into or out of the 24-bit input shift
register.
4
A0
Address Input. Sets the first LSB of the 7-bit slave address.
5
A1
Address Input. Sets the second LSB of the 7-bit slave address.
6
VOUT7
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
7
VOUT6
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
8
VOUT5
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
9
VOUT4
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
10, 16
NIC
No Internal Connection.
11
GND
Ground Reference Point for All Circuitry on the Device.
12
LDAC
Load DAC. LDAC operates in two modes, asynchronously and synchronously. Pulsing this pin low allows any or all
DAC registers to be updated if the input registers have new data, which allows all DAC outputs to simultaneously
update. This pin can also be tied permanently low.
13
SDA
Serial Data Input. This pin is used in conjunction with the SCL line to clock data into or out of the 24-bit input shift
register. SDA is a bidirectional, open-drain data line that must be pulled to the supply with an external pull-up resistor.
14
RESET
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC pulses are ignored.
When RESET is activated, the input register and the DAC register are updated with zero scale or midscale, depending
on the state of the RSTSEL pin.
15
VREF
Reference Input Voltage.
17
VOUT3
Analog Output Voltage from DAC 3. The output amplifier has rail-to-rail operation.
18
VOUT2
Analog Output Voltage from DAC 2. The output amplifier has rail-to-rail operation.
19
VOUT1
Analog Output Voltage from DAC 1. The output amplifier has rail-to-rail operation.
20
VOUT0
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.
EPAD
Exposed Pad. The exposed pad must be tied to GND.


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