RF Agile Transceiver

Data Sheet

AD9364

Rev. C

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FEATURES

RF 1 × 1 transceiver with integrated 12-bit DACs and ADCs

Band: 70 MHz to 6.0 GHz

Supports time division duplex (TDD) and frequency division

duplex (FDD) operation

Tunable channel bandwidth (BW): <200 kHz to 56 MHz

3-band receiver: 3 differential or 6 single-ended inputs

Superior receiver sensitivity with a noise figure of <2.5 dB

Rx gain control

Real-time monitor and control signals for manual gain

Independent automatic gain control

2-band differential output transmitter

Highly linear broadband transmitter

Tx EVM: ≤−40 dB

Tx noise: ≤−157 dBm/Hz noise floor

Tx monitor: ≥66 dB dynamic range with 1 dB accuracy

Integrated fractional-N synthesizers

2.4 Hz maximum local oscillator (LO) step size

Multichip synchronization

CMOS/LVDS digital interface

APPLICATIONS

Point to point communication systems

Femtocell/picocell/microcell base stations

General-purpose radio systems

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

GENERAL DESCRIPTION

The AD9364 is a high performance, highly integrated radio fre-

quency (RF) Agile Transceiver™ designed for use in 3G and 4G base

station applications. Its programmability and wideband capability

make it ideal for a broad range of transceiver applications.

The device combines an RF front end with a flexible mixed-signal

baseband section and integrated frequency synthesizers, simpli-

fying design-in by providing a configurable digital interface to a

processor. The AD9364 operates in the 70 MHz to 6.0 GHz range,

covering most licensed and unlicensed bands. Channel bandwidths

from less than 200 kHz to 56 MHz are supported.

The direct conversion receiver has state-of-the-art noise figure

and linearity. The receive (Rx) subsystem includes independent

automatic gain control (AGC), dc offset correction, quadrature

correction, and digital filtering, thereby eliminating the need for

these functions in the digital baseband. The AD9364 also has

flexible manual gain modes that can be externally controlled.

Two high dynamic range ADCs digitize the received I and Q

signals and pass them through configurable decimation filters

and 128-tap FIR filters to produce a 12-bit output signal at the

appropriate sample rate.

The transmitter uses a direct conversion architecture that achieves

high modulation accuracy with ultralow noise. This transmitter

design produces a Tx EVM of ≤−40 dB, allowing significant system

margin for the external power amplifier (PA) selection. The on-

board transmit (Tx) power monitor can be used as a power

detector, enabling highly accurate Tx power measurements.

The fully integrated phase-locked loops (PLLs) provide low

power fractional-N frequency synthesis for all Rx and Tx channels.

All VCO and loop filter components are integrated.

The core of the AD9364 can be powered directly from a 1.3 V

regulator. The IC is controlled via a standard 4-wire serial port and

four real-time input control pins. Comprehensive power-down

modes are included to minimize power consumption during

normal use. The AD9364 is packaged in a 10 mm × 10 mm,

144-ball chip scale package ball grid array (CSP_BGA).

AD9364

RXB_P,

RXB_N

P1_[D11:D0]/

RX_[D5:D0]

P0_[D11:D0]/

TX_[D5:D0]

RADIO

SWITCHING

RXA_P,

RXA_N

RXC_P,

RXC_N

TX_MON

Rx LO

Tx LO

TXA_P,

TXA_N

TXB_P,

TXB_N

CTRL

AUXDACx

XTALN

AUXADC

CTRL

SPI

GPO

PLLs

CLK_OUT

DAC

ADC

NOTES

1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0],

AND RADIO SWITCHING CONTAIN MULTIPLE PINS.