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AD9528BCPZ Datasheet(PDF) 9 Page - Analog Devices |
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AD9528BCPZ Datasheet(HTML) 9 Page - Analog Devices |
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9 / 68 page  AD9528 Data Sheet Rev. C | Page 8 of 67 OUTPUT TIMING ALIGNMENT CHARACTERISTICS Table 9. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT TIMING SKEW Delay off on all outputs, maximum deviation between rising edges of outputs; all outputs are on and in HSTL mode, unless otherwise noted PLL1 Outputs PLL1 to PLL1 17 100 ps PLL1 clock to PLL1 clock PLL1 to SYSREF 17 100 ps SYSREF retimed by PLL1 clock PLL1 to SYSREF 361 510 ps SYSREF not retimed by any clock PLL1 to SYSREF 253 1150 ps SYSREF retimed by PLL2 clock PLL1 to PLL2 257 1000 ps PLL1 clock to PLL2 clock PLL2 Outputs PLL2 to PLL2 20 165 ps PLL2 clock to PLL2 clock PLL2 to SYSREF 20 165 ps SYSREF retimed by PLL2 clock PLL2 to SYSREF 620 750 ps SYSREF not retimed by any clock PLL2 to SYSREF 253 1150 ps SYSREF retimed by PLL1 clock PLL2 to PLL1 257 1000 ps PLL2 clock to PLL1 clock OUTPUT DELAY ADJUST Enables digital and analog delay capability Coarse Adjustable Delay 32 Steps Resolution step is the period of VCO RF divider (M1) output/2 Fine Adjustable Delay 15 Steps Resolution step Resolution Step 31 ps Insertion Delay 425 ps Analog delay enabled and delay setting equal to zero SYSREF_IN, SYSREF_IN, VCXO_IN, AND VCXO_IN TIMING CHARACTERISTICS Table 10. Parameter Min Typ Max Unit Test Conditions/Comments PROPAGATION LATENCY OF VCXO PATH 1.92 2.3 2.7 ns VCXO input to device clock output, not retimed PROPAGATION LATENCY OF SYSREF PATH 1.83 2.2 2.6 ns SYSREF input to SYSREF output, not retimed RETIMED WITH DEVICE CLOCK Setup Time of External SYSREF Relative to Device Clock Output −1.13 ns Given a SYSREF input clock rate equal to 122.88 MHz Hold Time of External SYSREF Relative to Device Clock Output 0.7 ns RETIMED WITH VCXO Setup Time of External SYSREF Relative to VCXO Input −0.21 ns Hold Time of External SYSREF Relative to VCXO 0.09 ns CLOCK OUTPUT ABSOLUTE PHASE NOISE—DUAL LOOP MODE Application examples are based on a typical setups (see Table 2) using an external 122.88 MHz VCXO (Crystek CVHD-950); reference = 122.88 MHz; channel divider = 10 or 1; PLL2 loop bandwidth (LBW) = 450 kHz. Table 11. Parameter Min Typ Max Unit Test Conditions/Comments HSTL OUTPUT f OUT = 122.88 MHz 10 Hz Offset −87 dBc/Hz 100 Hz Offset −106 dBc/Hz 1 kHz Offset −126 dBc/Hz 10 kHz Offset −135 dBc/Hz 100 kHz Offset −139 dBc/Hz |
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