TLC3574, TLC3578, TLC2574, TLC2578

5V ANALOG, 3/5V DIGITAL, 14/12BIT, 200KSPS, 4/8CHANNEL

SERIAL ANALOGTODIGITAL CONVERTERS WITH ±10V INPUTS

SLAS262C − OCTOBER 2000 − REVISED MAY 2003

23

POST OFFICE BOX 655303

sampling period (continued)

Normal Long Sampling Mode: It is the same as normal short sampling, except that it lasts 44 SCLKs periods

to complete the sampling.

Extended Sampling Mode: The external signal, CSTART, triggers sampling and conversion. SCLK is not used

for sampling. SCLK is also not needed for conversion if the internal conversion clock is selected. The falling edge

of CSTART begins the sampling of the selected analog input. The sampling continues while CSTART is low.

The rising edge of CSTART ends the sampling, and starts the conversion (with about 15 ns internal delay). The

occurrence of CSTART is independent of SCLK clock, CS, and FS. However, the first CSTART cannot occur

before the rising edge of the 11th SCLK. In other words, the falling edge of first CSTART can happen at or after

the rising edge of 11th SCLK , but not before. The device enters the extended sampling mode at the falling edge

of CSTART and exits this mode once CSTART goes to high followed by two consecutive falling edges of CS

or two consecutive rising edges of FS (such as one read data operations followed by WRITE CFR). The first

CS or FS does not cause conversion. Extended mode is used when a fast SCLK is not suitable for sampling,

or when extended sampling period is needed to accommodate different input signal source impedance.

conversion period

The conversion period is the third portion of the operation cycle. It begins after the falling edge of 16th SCLK

for the normal short sampling mode, or after the falling edge of 48th SCLK for the normal long sampling, or on

the rising edge of CSTART (with 15 ns internal delay) for the extended sampling mode.

The conversion takes 18 conversion clocks plus 15 ns for TLC3574/78, 13 conversion clocks plus 15 ns for the

TLC2574/78. The conversion clock source can be an internal oscillator, OSC, or an external clock, SCLK. The

conversion clock is equal to the internal OSC if the internal clock is used, or equal to four SCLKs when the

external clock is programmed. To avoid the premature termination of conversion, enough time for the conversion

must be allowed between consecutive triggers. EOC goes to low at the beginning of the conversion period and

goes to high at the end of the conversion period. INT goes to low at the end of this period, too.

conversion mode

Four different conversion modes (mode 00, 01, 10, 11) are available. The operation of each mode is slightly

different, depending on how the converter samples and what host interface is used. Do not mix different types

of triggers throughout the repeat or sweep operations.

ONE SHOT Mode (Mode 00): Each operation cycle performs one sampling and one conversion for the selected

channel. FIFO is not used. When EOC is selected, it is generated while the conversion period is in progress.

Otherwise, INT is generated after the conversion is done. The result is output through the SDO pin during the

next select/conversion operation.

REPEAT Mode (Mode 01): Each operation cycle performs multiple samplings and conversions for a fixed

channel selected according to the 4-bit command. The results are stored in the FIFO. The number of samples

to be taken equals the FIFO threshold programmed via D[1:0] in CFR register. Once the threshold is reached,

INT is generated, and the operation ends. If the FIFO is not read after the conversions, the data is replaced in

the next operation. The operation of this mode starts with the WRITE CFR commands to set conversion mode

01, then the SELECT/CONVERSION commands, followed by a number of samplings and conversions of the

fixed channel (triggered by CS, FS, or CSTART) until the FIFO threshold is hit. If CS or FS triggers the sampling,

the data on SDI must be any one of the SELECT CHANNEL commands. However, this data is a dummy code

for setting the converter in conversion state. It does not change the existing channel selection set at the start

of the operation until the FIFO is full. After the operation finishes, the host can read the FIFO, then reselect the

channel and start the next REPEAT operation again; or immediately reselect the channel and start next REPEAT

operation (by issuing CS or FS or CSTART); or reconfigure the converter then start new operation according

to the new setting. If CSTART triggers the sampling, host can also immediately start the next REPEAT operation

(on the current channel) after the FIFO is full. Besides, if FS initiates the operation and CSTART triggers the

samplings and conversions, CS must not toggle during the conversion. This mode allows the host to set up the

converter, continue monitoring a fixed input, and to get a set of samples as needed.