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MC908QL2V Datasheet(PDF) 65 Page - Motorola, Inc |
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MC908QL2V Datasheet(HTML) 65 Page - Motorola, Inc |
65 / 222 page Functional Description MC68HC908QL4 • MC68HC908QL3 • MC68HC908QL2 Data Sheet, Rev. 4 Freescale Semiconductor 65 LVIPWRD — LVI Power Disable Bit LVIPWRD disables the LVI module. 1 = LVI module power disabled 0 = LVI module power enabled LVITRIP — LVI Trip Point Selection Bit LVITRIP selects the voltage operating mode of the LVI module. The voltage mode selected for the LVI should match the operating VDD for the LVI’s voltage trip points for each of the modes. 1 = LVI operates for a 5-V protection 0 = LVI operates for a 3.3-V protection NOTE The LVITRIP bit is cleared by a power-on reset (POR) only. Other resets will leave this bit unaffected. SSREC — Short Stop Recovery Bit SSREC enables the CPU to exit stop mode with a delay of 32 BUSCLKX4 cycles instead of a 4096 BUSCLKX4 cycle delay. 1 = Stop mode recovery after 32 BUSCLKX4 cycles 0 = Stop mode recovery after 4096 BUSCLKX4 cycles NOTE Exiting stop mode by an LVI reset will result in the long stop recovery. STOP — STOP Instruction Enable Bit STOP enables the STOP instruction. 1 = STOP instruction enabled 0 = STOP instruction treated as illegal opcode COPD — COP Disable Bit COPD disables the COP module. 1 = COP module disabled 0 = COP module enabled |
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Descripción similar - MC908QL2V |
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