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DLHR-L60G-E1BD-C-NAV8 Datasheet(PDF) 9 Page - All Sensors Corporation |
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DLHR-L60G-E1BD-C-NAV8 Datasheet(HTML) 9 Page - All Sensors Corporation |
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9 / 16 page  All Sensors DS-0350 Rev A Figure 5 - SPI Timing Diagram Figure 6 - I2C Timing Diagram Interface Timing Diagrams Page 9 SCLK MISO SS tSSCLK (HI•Z) tCLKD tHIGH tLOW (HI•Z) tCLKSS tSSZ tIDLE MOSI tSSSO (don't care) tDSU tDH don't care PARAMETER SYMBOL MIN TYP MAX UNITS SCLK frequency (1) fSCLK 0.05 - 5 MHz SS low to first clock edge tSSCLK 120 - - ns SS low to serial out tSSSO -- - 20 ns Clock to data out tCLKD 8 - 32 ns SCLK low width tLOW 100 - - ns SCLK high width tHIGH 100 - - ns Data setup to clock tDSU 50 - - ns Data hold after clock tDH 50 - - ns Last clock to rising SS tCLKSS 0 - - ns SS high to output hi-Z tSSZ -- - 20 ns Bus idle time tIDLE 250 - - ns (1) Maximum by design, tested to 1.0 MHz. SCL SDA tHSTA tHDAT tSUDAT tHIGH tLOW t P T S U S tIDLE t A T S U S PARAMETER SYMBOL MIN TYP MAX UNITS SCL frequency fSCL 100 - 400 KHz SCL low width tLOW 1.3 - - us SCL high width tHIGH 0.6 - - us Start condition setup tSUSTA 0.6 - - us Start condition hold tHSTA 0.6 - - us Data setup to clock tSUDAT 0.1 - - us Data hold to clock tHDAT 0 - - us Stop condition setup tSUSTP 0.6 - - us Bus idle time tIDLE 2.0 - - us |
Número de pieza similar - DLHR-L60G-E1BD-C-NAV8 |
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Descripción similar - DLHR-L60G-E1BD-C-NAV8 |
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