ADAQ7988 datasheet(11/49 Pages) AD

No. de pieza	ADAQ7988

Descripción Electrónicos	16-Bit, 1 MSPS, Integrated Data Acquisition Subsystem

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Fabricante Electrónico	AD [Analog Devices]

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Data Sheet

ADAQ7980/ADAQ7988

Rev. 0 | Page 11 of 49

TIMING SPECIFICATIONS

VDD = 3.5 V to 10 V, VIO = 1.7 V to 5.5 V, and TA = −55°C to +125°C, unless otherwise noted In addition to Figure 2 and Figure 3, see

Figure 72, Figure 74, Figure 76, Figure 78, Figure 80, and Figure 82 for the additional timing diagrams detailed in Table 6.

Table 6.

Parameter

Symbol

Min

Typ

Max

Unit

CONVERSION TIME: CNV RISING EDGE TO DATA AVAILABLE

tCONV

VIO Above 3.0 V (ADAQ7980)

500

710

ns

VIO Above 1.7 V (ADAQ7980)

500

800

ns

ADAQ7988

500

1200

ns

ACQUISITION PHASE1

tACQ

ns

ADAQ7980

290

ns

ADAQ7988

800

ns

TIME BETWEEN CONVERSIONS

tCYC

VIO Above 3.0 V (ADAQ7980)

1000

ns

VIO Above 1.7 V (ADAQ7980)

1200

ns

VIO Above 1.7 V (ADAQ7988)

2000

ns

CS MODE

CNV Pulse Width

tCNVH

10

ns

SCK Period

tSCK

VIO Above 4.5 V

10.5

ns

VIO Above 3.0 V

12

ns

VIO Above 1.7 V

22

ns

CNV or SDI Low to SDO D15 MSB Valid

tEN

VIO Above 3.0 V

10

ns

VIO Above 1.7 V

40

ns

CNV or SDI High or Last SCK Falling Edge to SDO High Impedance

tDIS

20

ns

SDI Valid Hold Time from CNV Rising Edge

tHSDICNV

VIO Above 3.0 V

2

ns

VIO Above 1.7 V

10

ns

CHAIN MODE

SCK Period

tSCK

VIO Above 4.5 V

11.5

ns

VIO Above 3.0 V

13

ns

VIO Above 1.7 V

23

ns

SDI Valid Hold Time from CNV Rising Edge

tHSDICNV

0

ns

SCK Valid Setup Time from CNV Rising Edge

tSSCKCNV

5

ns

SCK Valid Hold Time from CNV Rising Edge

tHSCKCNV

5

ns

SDI Valid Setup Time from SCK Falling Edge

tSSDISCK

2

ns

SDI Valid Hold Time from SCK Falling Edge

tHSDISCK

3

ns

SDI High to SDO High (with Busy Indicator)

tDSDOSDI

VIO Above 3.0 V

15

ns

VIO Above 1.7 V

22

ns

SCK

Low Time

tSCKL

VIO Above 3.0 V

4.5

ns

VIO Above 1.7 V

6

ns

High Time

tSCKH

VIO Above 3.0 V

4.5

ns

VIO Above 1.7 V

6

ns

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